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74AC109

  

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一致 , 類似 74AC109
前一致 74AC109C* 74AC109M* 74AC109P* 74AC109S*
後一致 *C74AC109 *N74AC109 *D74AC109 *V74AC109
含む *74AC109* *74AC109D* *74AC109E* *74AC109F* *74AC109M* *74AC109N* *74AC109P*
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74AC109_2001 [Dual JK Positive Edge−Triggered Flip−Flop ]

other parts : 74ACT109_2001  MC74AC109_2001  MC74ACT109_2001  MC74AC109N_2001  MC74AC109D_2001  MC74AC109DR2_2001  MC74AC109DT_2001 

ON-Semiconductor
ON Semiconductor

The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

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74AC109 [Dual JK Positive Edge−Triggered Flip−Flop ]

other parts : 74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DT 

ONSEMI
ON Semiconductor

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

View
74AC109 [Dual JK Positive Edge−Triggered Flip−Flop ]

other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74AC109M 

ON-Semiconductor
ON Semiconductor

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

View
74AC109 [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
74AC109 [Dual JK positive edge-triggered flip-flop ]

other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109N  MC74ACT109  MC74ACT109D  MC74ACT109N 

Motorola
Motorola => Freescale

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

View
74AC109SC [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SCX  74AC109SJ 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
74AC109PC [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
74AC109CW [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
74AC109SJ [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109  74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
74AC109MTC [Dual JK Positive Edge-Triggered Flip-Flop ]

other parts : 74AC109  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs

View
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