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74ACT109

  

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일치하는 74ACT109
시작하는 74ACT109* 74ACT109C* 74ACT109M* 74ACT109P* 74ACT109S*
끝나는 *C74ACT109 *N74ACT109 *D74ACT109 *V74ACT109
포함하는 *N74ACT109* *C74ACT109* *D74ACT109*

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Motorola
Motorola => Freescale
74ACT109 Dual JK positive edge-triggered flip-flop

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of


other parts : 74AC109 MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N 
ON-Semiconductor
ON Semiconductor
74ACT109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are


other parts : 74AC109 MC74AC109 MC74AC109D MC74AC109DR2 MC74AC109DT MC74AC109DTR2 MC74AC109M MC74AC109MEL MC74AC109N MC74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109CW 
TI
Texas Instruments
74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

description/ordering information
The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not


other parts : 54ACT109 CD54ACT109 CD54ACT109F3A CD74ACT109 CD74ACT109E CD74ACT109EE4 CD74ACT109M CD74ACT109M96 CD74ACT109M96E4 CD74ACT109M96G4 
Fairchild
Fairchild Semiconductor
74ACT109SC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109PC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109CW Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109MTC Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109SCX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 
Fairchild
Fairchild Semiconductor
74ACT109PCX Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109 74AC109MTC 74AC109MTCX 74AC109PC 74AC109PCX 74AC109SC 74AC109SCX 74AC109SJ 74AC109SJX 74ACT109 

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