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74ACT74MTCX

  

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74ACT74MTCX_2008 [Dual D-Type Positive Edge-Triggered Flip-Flop ]

other parts : 74AC74_2008  74ACT74_2008  74AC74SC_2008  74AC74SJ_2008  74AC74MTC_2008  74ACT74SC_2008  74ACT74SJ_2008  74ACT74MTC_2008  74AC74SCX_2008  74AC74SJX_2008 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:
■ LOW input to SD (Set) sets Q to HIGH level
■ LOW input to CD (Clear) sets Q to LOW level
■ Clear and Set are independent of clock
■ Simultaneous LOW on CD and SD makes both Q and Q HIGH

Features
■ ICC reduced by 50%
■ Output source/sink 24mA
■ ACT74 has TTL-compatible inputs

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74ACT74MTCX [Dual D-Type Positive Edge-Triggered Flip-Flop ]

other parts : 74AC74  74AC74MTC  74AC74MTCX  74AC74MTCX_NL  74AC74PC  74AC74SC  74AC74SCX  74AC74SJX  74AC74SC_NL  74AC74SJ 

Fairchild
Fairchild Semiconductor

General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the  Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
   LOW input to SD(Set) sets Q to HIGH level
   LOW input to CD(Clear) sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CDand SDmakes both Q and Q HIGH

Features
■ICCreduced by 50%
■Output source/sink 24 mA
■ACT74 has TTL-compatible inputs

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