Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site

74HCT107

   Datasheet
Match, Like 74HCT107 74HCT107D 74HCT107N 74HCT107U
Start with 74HCT107-* 74HCT107D* 74HCT107N* 74HCT107P* 74HCT107U*
End *D74HCT107
Included *74HCT107E*

74HCT107 [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HC107U  74HC107N  74HC107D  74HC107DB  74HC107PW  74HCT107D  74HCT107N  74HCT107U  74HCT107DB 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107D [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107U  74HC107N  74HC107D  74HC107PW  74HC107DB  74HCT107N  74HCT107U  74HCT107DB 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107N [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107U  74HC107N  74HC107D  74HC107PW  74HC107DB  74HCT107D  74HCT107U  74HCT107DB 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107U [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107U  74HC107N  74HC107D  74HC107PW  74HC107DB  74HCT107D  74HCT107N  74HCT107DB 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107DB [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107U  74HC107N  74HC107D  74HC107PW  74HC107DB  74HCT107D  74HCT107N  74HCT107U 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107PW [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107U  74HC107N  74HC107D  74HC107PW  74HC107DB  74HCT107D  74HCT107N  74HCT107U 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• Output capability: standard
• ICC category: flip-flops

 

View
74HCT107 [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HC107D  74HCT107D  74HC107DB  74HC107PW 

NXP
NXP Semiconductors.

General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
   
Features and benefits
■ Complies with JEDEC standard no. 7A
■ Input levels:
    ◆ The 74HC107: CMOS levels
    ◆ The 74HCT107: TTL levels
■ ESD protection:
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from -40°C to +85°C and from -40°C to +125°C
   

View
74HCT107D [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107  74HCT107  74HC107D  74HC107DB  74HC107PW 

NXP
NXP Semiconductors.

General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
   
Features and benefits
■ Complies with JEDEC standard no. 7A
■ Input levels:
    ◆ The 74HC107: CMOS levels
    ◆ The 74HCT107: TTL levels
■ ESD protection:
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from -40°C to +85°C and from -40°C to +125°C
   

View
74HCT107-Q100 [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107-Q100  74HC107D-Q100  74HC107PW-Q100  74HCT107D-Q100 

NXP
NXP Semiconductors.

General description
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits
■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)
♦ Specified from 40 C to +85 C and from 40 C to +125 C
■ Input levels:
♦ For 74HC107-Q100: CMOS level
♦ For 74HCT107-Q100: TTL level
■ Complies with JEDEC standard no. 7A
■ ESD protection:
♦ MIL-STD-883, method 3015 exceeds 2000 V
♦ HBM JESD22-A114F exceeds 2000 V
♦ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
■ Multiple package options

 

View
74HCT107D-Q100 [Dual JK flip-flop with reset; negative-edge trigger ]

other parts : 74HC107-Q100  74HC107D-Q100  74HCT107-Q100  74HC107PW-Q100 

NXP
NXP Semiconductors.

General description
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits
■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)
♦ Specified from 40 C to +85 C and from 40 C to +125 C
■ Input levels:
♦ For 74HC107-Q100: CMOS level
♦ For 74HCT107-Q100: TTL level
■ Complies with JEDEC standard no. 7A
■ ESD protection:
♦ MIL-STD-883, method 3015 exceeds 2000 V
♦ HBM JESD22-A114F exceeds 2000 V
♦ MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
■ Multiple package options

 

View
1


HOME


Key Word

System  Voltage  Analog  Audio  Axial  Battery  Bipolar  Bridge  Camera  Chip  Clock  Color  Connector  Control  Controller  Converter  Counter  Crystal  Decoder  Digital 

Share Link : 
Language : 한국어    日本語    русский    简体中文    español
@ 2015 - 2018  [ Home ][ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]