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ADS6242

  

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ADS6242 [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6245  AZ6243  AZ6242  AZ6244  ADS6243  ADS6245  ADS6244  ADS6242IRGZR  ADS6244IRGZR  ADS6243IRGZT 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242 [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6242  AZ6243  AZ6244  AZ6245  ADS6245  ADS6244  ADS6243  ADS6244IRGZR  ADS6243IRGZT  ADS6245IRGZR 

Texas-Instruments
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
ADS624X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR Trade-
   Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
   Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)
  
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZR [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6244  AZ6245  AZ6243  AZ6242  ADS6243  ADS6245  ADS6244  ADS6242  ADS6242IRGZT  ADS6244IRGZR 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZR [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6242  AZ6243  AZ6245  AZ6244  ADS6242  ADS6245  ADS6244  ADS6243  ADS6244IRGZR  ADS6245IRGZR 

Texas-Instruments
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
ADS624X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR Trade-
   Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
   Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)
  
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZT [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6245  AZ6244  AZ6243  AZ6242  ADS6243  ADS6244  ADS6245  ADS6242  ADS6245IRGZR  ADS6242IRGZR 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZT [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6242  AZ6243  AZ6245  AZ6244  ADS6242  ADS6245  ADS6244  ADS6243  ADS6244IRGZR  ADS6245IRGZR 

Texas-Instruments
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
ADS624X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C).

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR Trade-
   Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
   Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)
  
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZ25 [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6244  AZ6245  AZ6243  AZ6242  ADS6243  ADS6245  ADS6244  ADS6242  ADS6242IRGZT  ADS6244IRGZR 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZRG4 [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6244  AZ6245  AZ6243  AZ6242  ADS6245  ADS6243  ADS6244  ADS6242  ADS6242IRGZT  ADS6242IRGZR 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
ADS6242IRGZTG4 [DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS ]

other parts : AZ6244  AZ6245  AZ6243  AZ6242  ADS6245  ADS6243  ADS6244  ADS6242  ADS6242IRGZT  ADS6242IRGZR 

TI
Texas Instruments

DESCRIPTION
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5 dB Coarse Gain and up to 6 dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVpp
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 48 QFN Package (7 mm × 7 mm)
• Pin Compatible 12-Bit Family (ADS622X -
   SLAS543A)
• Feature Compatible Quad Channel Family
   (ADS644X - SLAS531A and ADS642X -
   SLAS532A)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

View
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