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DM74LS109A

  

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National-Semiconductor
National ->Texas Instruments
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset


other parts : 54LS109 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109AM DM74LS109AN DM74LS109AJ 
Fairchild
Fairchild Semiconductor
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset


other parts : DM74LS109AM DM74LS109AN DM74LS109AMX 
National-Semiconductor
National ->Texas Instruments
DM74LS109AM Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset


other parts : 54LS109 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN DM74LS109AJ 
National-Semiconductor
National ->Texas Instruments
DM74LS109AN Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset


other parts : 54LS109 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AJ 
Fairchild
Fairchild Semiconductor
DM74LS109AM Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset


other parts : DM74LS109A DM74LS109AN DM74LS109AMX 
Fairchild
Fairchild Semiconductor
DM74LS109AN Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset


other parts : DM74LS109A DM74LS109AM DM74LS109AMX 
National-Semiconductor
National ->Texas Instruments
DM74LS109AJ Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset


other parts : 54LS109 54LS109DMQB 54LS109FMQB DM54LS109A DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AM DM74LS109AN 
National-Semiconductor
National ->Texas Instruments
DM74LS109AJ Triple 3-Input NAND Gates

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset

National-Semiconductor
National ->Texas Instruments
DM74LS109AJ Triple 3-Input NAND Gates

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset

Fairchild
Fairchild Semiconductor
DM74LS109AM Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level on the preset


other parts : DM74LS109AMX DM74LS109AN 

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