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MC100EL33D_2008 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2008
MC100EL33_2008
MC10EL33D_2008
MC10EL33DG_2008
MC10EL33DT_2008
MC100EL33DG_2008
MC10EL33DTG_2008
MC100EL33DT_2008
MC10EL33DR2_2008
MC10EL33MNR4_2008
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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MC100EL33D [5V ECL ÷4 Divider ]
other parts : MC10EL33
MC10EL33D
MC100EL33
MC10EL33DT
MC10EL33DG
MC100EL33DT
MC10EL33DTG
MC100EL33DG
MC10EL33DR2
MC10EL33DR2G
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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MC100EL33DG_2008 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2008
MC100EL33_2008
MC10EL33D_2008
MC10EL33DG_2008
MC100EL33D_2008
MC10EL33DT_2008
MC10EL33DTG_2008
MC100EL33DT_2008
MC10EL33DR2_2008
MC10EL33MNR4_2008
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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MC100EL33DG_2016 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2016
MC100EL33_2016
MC10EL33DG_2016
MC10EL33DTG_2016
MC10EL33DR2G_2016
MC100EL33DTG_2016
MC100EL33DR2G_2016
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection:
♦ > 1 kV Human Body Model
♦ > 100 V Machine Model
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
♦ Level 1 for SOIC−8 NB
♦ Level 3 for TSSOP−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
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MC100EL33DG [5V ECL ÷4 Divider ]
other parts : MC10EL33
MC10EL33D
MC100EL33
MC10EL33DT
MC100EL33D
MC10EL33DG
MC100EL33DT
MC10EL33DTG
MC10EL33DR2
MC10EL33DR2G
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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MC100EL33DT_2008 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2008
MC100EL33_2008
MC10EL33D_2008
MC10EL33DG_2008
MC100EL33D_2008
MC10EL33DT_2008
MC10EL33DTG_2008
MC100EL33DG_2008
MC10EL33DR2_2008
MC10EL33MNR4_2008
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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View
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MC100EL33DT [5V ECL ÷4 Divider ]
other parts : MC10EL33
MC10EL33D
MC100EL33
MC10EL33DT
MC100EL33D
MC10EL33DG
MC10EL33DTG
MC100EL33DG
MC10EL33DR2
MC10EL33DR2G
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
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View
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MC100EL33DR2_2008 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2008
MC100EL33_2008
MC10EL33D_2008
MC10EL33DG_2008
MC100EL33D_2008
MC10EL33DT_2008
MC100EL33DT_2008
MC10EL33DTG_2008
MC100EL33DG_2008
MC10EL33DR2_2008
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
|
View
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MC100EL33DR2 [5V ECL ÷4 Divider ]
other parts : MC10EL33
MC10EL33D
MC100EL33
MC10EL33DT
MC100EL33D
MC10EL33DG
MC100EL33DT
MC100EL33DG
MC10EL33DR2
MC10EL33DTG
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
|
View
|
|
MC100EL33DTG_2008 [5V ECL ÷4 Divider ]
other parts : MC10EL33_2008
MC100EL33_2008
MC10EL33D_2008
MC10EL33DG_2008
MC100EL33D_2008
MC10EL33DT_2008
MC100EL33DT_2008
MC10EL33DTG_2008
MC100EL33DG_2008
MC10EL33DR2_2008
|
ON Semiconductor |
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
• ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on CLK(s) and R.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
|
View
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