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MC14043BF

  

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MC14043BF_2000 [CMOS MSI Quad R−S Latches ]

other parts : MC14043B_2000  MC14044B_2000  MC14043BD_2000  MC14044BD_2000  MC14043BCP_2000  MC14044BCP_2000  MC14043BDR2_2000  MC14043BFEL_2000  MC14044BDR2_2000 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R–S latches are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three–state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

• Double Diode Input Protection
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One
   Low–Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc

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MC14043BF [CMOS MSI Quad R−S Latches ] ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R–S latches are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three–state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

• Double Diode Input Protection
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One
   Low–Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc

View
MC14043BFEL_2000 [CMOS MSI Quad R−S Latches ]

other parts : MC14043B_2000  MC14044B_2000  MC14043BD_2000  MC14043BF_2000  MC14044BD_2000  MC14043BCP_2000  MC14044BCP_2000  MC14043BDR2_2000  MC14044BDR2_2000 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R–S latches are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three–state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

• Double Diode Input Protection
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One
   Low–Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc

View
MC14043BFEL [CMOS MSI Quad R−S Latches ]

other parts : MC14043B  MC14044B  MC14044BP  MC14043BD  MC14044BD  MC14043BP  MC14043BDG  MC14043BCP  MC14044BCP  MC14044BDG 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
   Low−Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Pb−Free Packages are Available*

View
MC14043BFR1 [CMOS MSI Quad R−S Latches ]

other parts : MC14043B  MC14044B  MC14044BP  MC14043BD  MC14044BD  MC14043BP  MC14043BDG  MC14043BCP  MC14044BCP  MC14044BDG 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
   Low−Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Pb−Free Packages are Available*

View
MC14043BFELG_2013 [CMOS MSI Quad R−S Latches ]

other parts : MC14043B_2013  MC14044B_2013  MC14043BDG_2013  MC14044BDG_2013  NLV14044BDG_2013  NLV14043BDG_2013  MC14043BCPG_2013  MC14044BCPG_2013  MC14043BDR2G_2013  MC14044BDR2G_2013 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
   Low−Power Schottky TTL Load Over the Rated Temperature
   Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable

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MC14043BFELG_2014 [CMOS MSI Quad R−S Latches ]

other parts : MC14043B_2014  MC14044B_2014  MC14043BDG_2014  MC14044BDG_2014  NLV14043BDG_2014  NLV14044BDG_2014  MC14043BDR2G_2014  MC14044BDR2G_2014  NLV14043BDR2G_2014  NLV14044BDR2G_2014 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
   Low−Power Schottky TTL Load Over the Rated Temperature
   Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant

View
MC14043BFELG [CMOS MSI Quad R−S Latches ]

other parts : MC14043B  MC14044B  MC14044BP  MC14043BD  MC14044BD  MC14043BP  MC14043BDG  MC14043BCP  MC14044BCP  MC14044BDG 

ON-Semiconductor
ON Semiconductor

The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.

Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
   Low−Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Pb−Free Packages are Available*

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