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MC74HC125ADTR2

  

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MC74HC125ADTR2 [Quad 3−State Noninverting Buffers ]

other parts : MC74HC125AN  MC74HC125ANG  MC74HC125AD  MC74HC125ADG  MC74HC125ADR2  MC74HC125ADR2G  MC74HC125ADT 

ON-Semiconductor
ON Semiconductor

Quad 3−State Noninverting Buffers
High−Performance Silicon−Gate CMOS

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The devices have four separate output enables that are active−low (HC125A) or active−high (HC126A).

Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Packages are Available

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MC74HC125ADTR2G [Quad 3-State Noninverting Buffers ]

other parts : MC74HC125A  MC74HC126A  MC74HC125ANG  MC74HC125ADG  MC74HC125ADR2G  MC74HC125ADTG  MC74HC126ANG 

ON-Semiconductor
ON Semiconductor

Quad 3-State Noninverting Buffers
High−Performance Silicon−Gate CMOS

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The devices have four separate output enables that are active−low (HC125A) or active−high (HC126A).

Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
   Unique Site and Control Change Requirements; AEC−Q100
   Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

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MC74HC125ADTR2G [Quad 3−State Noninverting Buffers ]

other parts : MC74HC125AN  MC74HC125ANG  MC74HC125AD  MC74HC125ADG  MC74HC125ADR2  MC74HC125ADR2G  MC74HC125ADT 

ON-Semiconductor
ON Semiconductor

Quad 3−State Noninverting Buffers
High−Performance Silicon−Gate CMOS

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The devices have four separate output enables that are active−low (HC125A) or active−high (HC126A).

Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Packages are Available

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