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Semtech
SemtechSemtech
PM8 Axial Leaded Hermetically Sealed Standard Recovery Rectifier Diode

Description
Quick reference data
  VR = 600V - 1000V
  IF = 2.0A
  trr = 3µS
  IR = 1.0µA
 
Features
♦ Avalanche capability
♦ High thermal shock resistance
♦ Glass passivated for hermetic sealing
♦ Low reverse leakage currents
♦ Low forward voltage drop

 


other parts : PM0 PM6 
PMC-Sierra
PMC-SierraPMC-Sierra
PM8380 4-Channel Multiplexer and Link Extender for SAS, SATA, Ethernet and FC

FEATURES
GENERAL - SATA AND SAS
• Four bi-directional 2:1 SATA or SAS multiplexer/demultiplexer.
• Compliant with SAS Internal and External specification.
• SATA Gen1i, Gen1x, Gen2i, Gen2x compliant.
• In the downstream direction, the QuadSMX 3G demuxes the initiator-side receive ports to either the A or B device-side transmit ports.
• In the upstream direction, the QuadSMX 3G selects either the A or B device-side receive port to output on the initiator-side transmit ports.
• Passes-thru out-of-band (OOB) signaling.
• Internal OOB detectors for COMSAS, COMRESET/COMINIT and COMWAKE.
• Provides port reordering to support standard SATA/SAS 4 channel connectors and easier PCB routing.

GENERAL - ETHERNET AND FIBRE CHANNEL
• Four channel bi-directional Gigabit Ethernet and 10 Gigabit Ethernet (XAUI) link extender and 2:1 serial multiplexer/demultiplexer.
• Four channel bi-directional 1G,2G and 10G Fibre Channel link extender and 2:1 serial multiplexer/demultiplexer
• Provides transmit redundancy for Ethernet and Fibre Channel Switch Applications. In this case,data is broadcast to both Port A and Port B.

HIGH-SPEED I/O
• 1.0 Gbit/s to 3.2 Gbit/s operation.
• Automatic amplitude control for SATA and SAS applications.
• Programmable receive equalization, transmit preemphasis and transmit output swing.
• Integrated resistive termination and receive AC coupling.
• Analog interfaces support SATA and SAS hot plug.

APPLICATIONS
• Host Bus Adapter.
• RAID controller.
• Ethernet (1GE and 10 GE XAUI) and Fibre Channel (1,2 and 10 GFC) link extender.
• Ethernet (1GE and 10 GE XAUI) and Fibre Channel (1,2 and 10 GFC) mux/demux.
• PCI Express, PCI Advanced Switching, ATCA, serial RapidIO, Infiniband, and HDTV link extender and mux/demux.

PMC-Sierra
PMC-SierraPMC-Sierra
PM8313 M13 MULTIPLEXER

FEATURES
• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.

Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.

APPLICATIONS
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format

 


other parts : PM8313-RI PM8313D3MX 
PMC-Sierra
PMC-SierraPMC-Sierra
PM8353 4-Channel 1.0-1.25 Gbps Transceiver

GENERAL DESCRIPTION
The QuadPHYTM is a Quad PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links. It provides four individual serial channels capable of operation at up to 1.25 Gbps each, which may be grouped together to form a single 5.0 Gbps bidirectional link. Each of the four primary channels has a corresponding secondary channel that can be enabled via the MDC/MDIO serial interface.

PMC-Sierra
PMC-SierraPMC-Sierra
PM8316 High Density 84-Channel T1/E1/J1 Framer with Integrated VT/TU Mappers and M13

FEATURES
The PM8316 TEMUX-84 is a 155 Mbit/s multi-channel T1/E1 Framer with integrated VT/TU Mappers and M13 Multiplexers.
• This monolithic device integrates:
   • 84 T1 framers
   • 63 E1 framers
   • Three SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mappers
   • Three full featured M13 multiplexers with DS3 framers
   • Three SONET/SDH DS3 mappers for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams
• Each SPE/STS-1 can be independently programmed for various T1, E1 or DS3 modes of operation.
• Supports wide range of T1, E1 and J1 framing formats.
• Supports M23 and C-bit parity DS3 formats.
• Stand-alone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload.
• Flexible line side and system side interface support :
   • Provides a 19.44 or 77.76 MHz SONET/SDH Add/Drop Telecom bus interface for seamless connection with PMC’s SONET/SDH devices.
   • Supports a byte serial Scaleable Bandwidth Interconnect (SBI™) bus interface at either 19.44 MHz or 77.76 MHz for high density system side device interconnection to PMC’s link layer products.
   • Supports 8 Mbit/s H-MVIP on the system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
   • Support for transparent virtual tributaries when SBI interface is used with SONET/SDH mapper.
   • Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to/from the SBI bus interface.
• Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
• Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
• Provides per link diagnostic and line loopbacks.
• Provides PRBS generators and detectors at DS3 and E3 rates and on each tributary for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T O.151, 0.152.
• Feature-rich functional software drivers available with device.
• Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

APPLICATIONS
• High density T1/E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• Channelized and Unchannelized DS3 Frame Relay Interfaces.
• Optical Access Equipment
• SONET/SDH Add Drop and Terminal Multiplexers.
• M13 Multiplexer/Demultiplexer Equipment.
• Digital Access Cross-Connect Systems

PMC-Sierra
PMC-SierraPMC-Sierra
PM8310 High Density T1/E1 Framer, VT/TU Mapper & M13 Mux with Integrated SONET/SDH Framers

PRODUCT OVERVIEW
The PM8310 TEMUX 336 is a high density T1/E1, DS3/E3 framer, VT/TU mapper, and M13 multiplexer with integrated SONET/SDH framers for OC-12/STM-4 and 4xOC-3/STM-1 applications. Feature integration and scalability make the TEMUX 336 ideal for use in ATCA/AMC line cards, voice and media gateways, routers, and multi-service and edge aggre gation switches.

PRODUCT HIGHLIGHTS
• 8 OC-3/STM-1 or 2 OC-12/STM-4 SONET/SDH framers
• 336 T1/252 E1 framers
• 12 M13 multiplexers, including support for G.747 multiplexing
• 12 DS3/E3 framers
• High order path processor for a SONET STS-12 or an SDH STM-4
• Tributary path processor for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Byte-synchronous and bit-asynchronous mapper for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Tributary path processor for 12 TU-3s
• Mapper for 12 DS3s or 12 E3s (TU-3 and AU-3)

APPLICATIONS
• ATCA/AMC-based line cards
• Voice and media gateways
• Wireless base station controllers (BSC) and radio network controllers (RNC)
• Routers and multi-service switches
• Edge aggregation switches
• Multi-service provisioning platforms


other parts : PM8310TEMUX336 
PMC-Sierra
PMC-SierraPMC-Sierra
PM8620 20G Narrowband Switch Element

Features
The Narrowband Switch Element 20G (NSE-20G):
• Implements a Scaleable Bandwidth Interconnect (SBI™) DS0 granularity Space switch.
• Implements a SONET/SDH VT1.5/VT2/TU11/TU12 granularity Space switch for the serial 777.6 MHz LVDS TelecomBus.
• With the allied SBS or SBS-lite device, implements a DS0 granularity Memory-Space Memory switch.
• Supports 32 STS-12 equivalent serial ports via 777.6 MHz, 8B/10B encoded LVDS links (each port can be either Serial TelecomBus or Serial SBI336S)
• When configured for SBI mode, switches DS0 or N*DS0 for all T1 and E1 tributaries and aggregate columns for switching T1, E1, TVT1.5, TVT2, DS3 and E3 tributaries.
• When configured for the serial 777.6 MHz TelecomBus interface, switches any SONET/SDH virtual tributary or tributary unit up to STS-1.
• Supports switching of arbitrary non-standard octet aggregates.
• Supports unicast, multicast, and broadcast for all switching modes.
• Provides 20 Gbit/s (258,048 DS0s, 10,752 T1s/VT1.5s, 8,064 E1s/VT2s, 384 DS3s/E3s) switching.
• Works with SBS devices that support up to four 19.44 MHz SBI buses or one 77.76 MHz SBI336 bus that communicates with PMC-Sierra’s SBI device family. Alternatively, the SBS and SBS-lite devices support up to four 19.44 MHz STS-3 TelecomBuses or one 77.76 MHz STS-12 TelecomBus for connection with PMC-Sierra’s SPECTRA™ family of devices.
• Can be combined in applications with PMC-Sierra’s CHESS™ Set devices (PM5374 TSE and PM5307 TBS).
• Supports a microprocessor interface which is used to configure/control the NSE, to make DS0-granularity switch settings.
• Supports clean error checked 8 Mbit/s full-duplex, in-band communications channels from the NSE’s attached microprocessor to the attached microprocessors of each of the 32 attached SBS336S devices. This channel is used to initialize and control the SBSs, or other such devices, and to implement call-establishment set-up changes.
• Supports JTAG for all non-LVDS signals.
• Requires dual power supplies at 1.8 V and 3.3 V.
• Packaged as a 480 ball UBGA.
• In conjunction with the SBS or SBS-lite, supports “1+1” and “1:N” fabric redundancy.

Applications
The PM8620 Narrowband Switch Element (NSE) supports a variety of flexible Layer 1 and Layer 2 architectures in combination with the following PMC-Sierra devices:
• PM8610 SBS and PM8611 SBS-lite (SBI Serializer and Memory switching stage)
• SBI bus devices (PM8315 TEMUX™/PM5365 TEMAP, FREEDM™ devices, S/UNI®-IMA devices, AAL1gator™ devices, and other future devices)
• CHESS chip set devices (PM5374 TSE, PM5307 TBS, PM5315 SPECTRA™-2488, and PM7390 S/UNI®-MACH48) These architectures include:
• T1/E1 SONET Add/Drop Multiplexers (ADMs)
• TDM ASAP applications
• PHY cards with DS0 (and above) level switching
• PSTN replacement switching cores, as part of any-service-any-port applications • Voice Gateways

 


other parts : PM8620-BIAP 
PMC
PMCPMC
PM8610 SBI Bus Serializer (SBS)

Description
The PM8610 SBI336 Bus Serializer (SBS) is a monolithic integrated circuit that implements conversion between a byte-serial 19.44 MHz SBI bus or 77.76 MHz SBI336 bus and a redundant
777.6 Mbit/s bit-serial 8B/10B-base SBI336S bus.
In TelecomBus mode, the SBS implements conversion between any 19.44 MHz TelecomBus or
77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial
TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input
DS0 to be output on any output DS0. The redundant 777.6 Mbit/s serial interfaces can be disabled
and a byte-wide SBI336 bus can be enabled in its place with all the DS0 level switching
capabilities.

 


other parts : PM8610-BIAP 
PMC-Sierra
PMC-SierraPMC-Sierra
PM8372 4-Port FC/GE Retimer and FC-AL Port Bypass Controller

GENERAL
• Supports 4 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel – Physical Interface (FC-PI) or 4 Gigabit Ethernet Retimers at 1.25 Gbit/s per IEEE 802.3z.
• Each port supports FC 1G or 2G rate detection/auto-selection.
• Supports Arbitrated Loop and Retimer configuration.
• Each port is independently selectable to perform retimer, reclocker or bypass-path function.
• Non-blocking crossconnect supports protection switching, broadcasting and multicasting.
• Automatic selection of retimer, reclocker or bypass-path function to minimize latency and jitter when a disk is bypassed.
• Per-port receive monitoring for loss of signal, error rate, and link level violations.
• Supports single-ended or differential 106.25 MHz reference clock REFCLK for Fibre Channel applications or 125 Mhz reference clock for Gigabit Ethernet applications.

HIGH-SPEED INTERFACE
• High-speed outputs with selectable preemphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
• Selectable receive input equalization for improved signal integrity.
• Minimized board footprint and improved signal integrity achieved because:
   • No external components are required to interface the high-speed signals to optics, coax, or serial backplanes using the internal AC coupling capacitors and terminating resistors.
   • Receive input termination of 100 Ω or 150 Ω differential is selectable.
   • Source output impedance of 100 Ω or 150 Ω differential is programmable.
  
APPLICATIONS
• FC-AL Nodes.
• RAID Storage Systems.
• JBOD Storage Systems.
• MBOD Storage Systems.
• SBOD Storage Systems.
• Fibre Channel Hubs.
• 1.0625/2.125 Gbit/s Backplanes.
• Gigabit Ethernet Retimer.

 

PMC
PMCPMC
PM8313 M13 MULTIPLEXER

FEATURES
• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.

Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.

APPLICATIONS
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format

 


other parts : PM8313-RI PM8313D3MX 

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