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 PM8
начиная PM80* PM81* PM83* PM86* PM89*
концы *FPM8 *SPM8 *VPM8 *3PM8 *OPM8 *JPM8 *RPM8 *MPM8 *EPM8 *DPM8 *IPM8
включая *PM8* *PM80* *PM8T*
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PM8 [Axial Leaded Hermetically Sealed Standard Recovery Rectifier Diode ]

other parts : PM0  PM6 

Semtech
Semtech Corporation

Description
Quick reference data
  VR = 600V - 1000V
  IF = 2.0A
  trr = 3µS
  IR = 1.0µA
 
Features
♦ Avalanche capability
♦ High thermal shock resistance
♦ Glass passivated for hermetic sealing
♦ Low reverse leakage currents
♦ Low forward voltage drop

 

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PM8311 [High Density T1/E1 Framer, VT/TU Mapper & M13 Mux with Integrated SONET/SDH Framers ]

other parts : PM8311TEMUX168 

PMC-Sierra
PMC-Sierra

PRODUCT OVERVIEW
The PM8311 TEMUX 168 is a single device integrating 2xOC-3/STM-1 SONET/SDH framers for working and protect links, 168/126 T1/E1 framers, 6 DS3/E3 framers, 6 M13/G.747 multiplexers and 6 VT/TU mappers.

PRODUCT HIGHLIGHTS
• 4 OC-3/STM-1 SONET/SDH framers
• 168 T1/126 E1 framers
• 6 M13 multiplexers, including support for G.747 multiplexing
• 6 DS3/E3 framers
• High order path processor for a SONET STS-3 or an SDH STM-1
• Tributary path processor for 168 VT1.5/TU-11s or 126 VT2/TU-12s
• Byte synchronous and bit asynchronous mapper for 168 VT1.5/TU-11s or 126 VT2/TU-12s
• Tributary path processor for 6 TU-3s
• Mapper for 6 DS3s or 6 E3s (TU-3 and AU-3)

INTERFACES
• Up to 4 SONET/SDH network interfaces
• SONET/SDH Transport and Path overhead interface
• Two 622-Mbit/s Extended Serial SONET/SDH Interfaces (ESSIs)
• Line-side serial interface for up to 6 DS3s or E3s
• System-side Scalable Bandwidth Interconnect (SBI) bus for high density interconnection of up to 168 T1 streams, 126 E1 streams, 6 DS3 streams, 6 E3 streams, or 6 arbitrary rate streams
• System-side serial interface for up to 6 DS3s or E3s
• Flexible bandwidth interface for up to 6 arbitrary rate ports
• 32 Mbit/s Synchronous TDM Interface (based on H-MVIP)
• Microprocessor- and IEEE 1149.1-compliant JTAG interface

PACKAGE
• 896-pin FCBGA (31 x 31 mm)
• Supports industrial temperature range (-40 ºC to 85 °C)

APPLICATIONS
• ATCA/AMC-based line cards
• Voice and media gateways
• Wireless base station controllers (BSC) and radio network controllers (RNC)
• Routers and multi-service switches
• Edge aggregation switches
• Multi-service provisioning platforms

 

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PM8380 [4-Channel Multiplexer and Link Extender for SAS, SATA, Ethernet and FC ] PMC-Sierra
PMC-Sierra

FEATURES
GENERAL - SATA AND SAS
• Four bi-directional 2:1 SATA or SAS multiplexer/demultiplexer.
• Compliant with SAS Internal and External specification.
• SATA Gen1i, Gen1x, Gen2i, Gen2x compliant.
• In the downstream direction, the QuadSMX 3G demuxes the initiator-side receive ports to either the A or B device-side transmit ports.
• In the upstream direction, the QuadSMX 3G selects either the A or B device-side receive port to output on the initiator-side transmit ports.
• Passes-thru out-of-band (OOB) signaling.
• Internal OOB detectors for COMSAS, COMRESET/COMINIT and COMWAKE.
• Provides port reordering to support standard SATA/SAS 4 channel connectors and easier PCB routing.

GENERAL - ETHERNET AND FIBRE CHANNEL
• Four channel bi-directional Gigabit Ethernet and 10 Gigabit Ethernet (XAUI) link extender and 2:1 serial multiplexer/demultiplexer.
• Four channel bi-directional 1G,2G and 10G Fibre Channel link extender and 2:1 serial multiplexer/demultiplexer
• Provides transmit redundancy for Ethernet and Fibre Channel Switch Applications. In this case,data is broadcast to both Port A and Port B.

HIGH-SPEED I/O
• 1.0 Gbit/s to 3.2 Gbit/s operation.
• Automatic amplitude control for SATA and SAS applications.
• Programmable receive equalization, transmit preemphasis and transmit output swing.
• Integrated resistive termination and receive AC coupling.
• Analog interfaces support SATA and SAS hot plug.

APPLICATIONS
• Host Bus Adapter.
• RAID controller.
• Ethernet (1GE and 10 GE XAUI) and Fibre Channel (1,2 and 10 GFC) link extender.
• Ethernet (1GE and 10 GE XAUI) and Fibre Channel (1,2 and 10 GFC) mux/demux.
• PCI Express, PCI Advanced Switching, ATCA, serial RapidIO, Infiniband, and HDTV link extender and mux/demux.

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PM8316 [High Density 84-Channel T1/E1/J1 Framer with Integrated VT/TU Mappers and M13 ] PMC-Sierra
PMC-Sierra

FEATURES
The PM8316 TEMUX-84 is a 155 Mbit/s multi-channel T1/E1 Framer with integrated VT/TU Mappers and M13 Multiplexers.
• This monolithic device integrates:
   • 84 T1 framers
   • 63 E1 framers
   • Three SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mappers
   • Three full featured M13 multiplexers with DS3 framers
   • Three SONET/SDH DS3 mappers for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams
• Each SPE/STS-1 can be independently programmed for various T1, E1 or DS3 modes of operation.
• Supports wide range of T1, E1 and J1 framing formats.
• Supports M23 and C-bit parity DS3 formats.
• Stand-alone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload.
• Flexible line side and system side interface support :
   • Provides a 19.44 or 77.76 MHz SONET/SDH Add/Drop Telecom bus interface for seamless connection with PMC’s SONET/SDH devices.
   • Supports a byte serial Scaleable Bandwidth Interconnect (SBI™) bus interface at either 19.44 MHz or 77.76 MHz for high density system side device interconnection to PMC’s link layer products.
   • Supports 8 Mbit/s H-MVIP on the system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
   • Support for transparent virtual tributaries when SBI interface is used with SONET/SDH mapper.
   • Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to/from the SBI bus interface.
• Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
• Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
• Provides per link diagnostic and line loopbacks.
• Provides PRBS generators and detectors at DS3 and E3 rates and on each tributary for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T O.151, 0.152.
• Feature-rich functional software drivers available with device.
• Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

APPLICATIONS
• High density T1/E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• Channelized and Unchannelized DS3 Frame Relay Interfaces.
• Optical Access Equipment
• SONET/SDH Add Drop and Terminal Multiplexers.
• M13 Multiplexer/Demultiplexer Equipment.
• Digital Access Cross-Connect Systems

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PM8310 [High Density T1/E1 Framer, VT/TU Mapper & M13 Mux with Integrated SONET/SDH Framers ]

other parts : PM8310TEMUX336 

PMC-Sierra
PMC-Sierra

PRODUCT OVERVIEW
The PM8310 TEMUX 336 is a high density T1/E1, DS3/E3 framer, VT/TU mapper, and M13 multiplexer with integrated SONET/SDH framers for OC-12/STM-4 and 4xOC-3/STM-1 applications. Feature integration and scalability make the TEMUX 336 ideal for use in ATCA/AMC line cards, voice and media gateways, routers, and multi-service and edge aggre gation switches.

PRODUCT HIGHLIGHTS
• 8 OC-3/STM-1 or 2 OC-12/STM-4 SONET/SDH framers
• 336 T1/252 E1 framers
• 12 M13 multiplexers, including support for G.747 multiplexing
• 12 DS3/E3 framers
• High order path processor for a SONET STS-12 or an SDH STM-4
• Tributary path processor for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Byte-synchronous and bit-asynchronous mapper for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Tributary path processor for 12 TU-3s
• Mapper for 12 DS3s or 12 E3s (TU-3 and AU-3)

APPLICATIONS
• ATCA/AMC-based line cards
• Voice and media gateways
• Wireless base station controllers (BSC) and radio network controllers (RNC)
• Routers and multi-service switches
• Edge aggregation switches
• Multi-service provisioning platforms

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PM8372 [4-Port FC/GE Retimer and FC-AL Port Bypass Controller ] PMC-Sierra
PMC-Sierra

GENERAL
• Supports 4 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel – Physical Interface (FC-PI) or 4 Gigabit Ethernet Retimers at 1.25 Gbit/s per IEEE 802.3z.
• Each port supports FC 1G or 2G rate detection/auto-selection.
• Supports Arbitrated Loop and Retimer configuration.
• Each port is independently selectable to perform retimer, reclocker or bypass-path function.
• Non-blocking crossconnect supports protection switching, broadcasting and multicasting.
• Automatic selection of retimer, reclocker or bypass-path function to minimize latency and jitter when a disk is bypassed.
• Per-port receive monitoring for loss of signal, error rate, and link level violations.
• Supports single-ended or differential 106.25 MHz reference clock REFCLK for Fibre Channel applications or 125 Mhz reference clock for Gigabit Ethernet applications.

HIGH-SPEED INTERFACE
• High-speed outputs with selectable preemphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
• Selectable receive input equalization for improved signal integrity.
• Minimized board footprint and improved signal integrity achieved because:
   • No external components are required to interface the high-speed signals to optics, coax, or serial backplanes using the internal AC coupling capacitors and terminating resistors.
   • Receive input termination of 100 Ω or 150 Ω differential is selectable.
   • Source output impedance of 100 Ω or 150 Ω differential is programmable.
  
APPLICATIONS
• FC-AL Nodes.
• RAID Storage Systems.
• JBOD Storage Systems.
• MBOD Storage Systems.
• SBOD Storage Systems.
• Fibre Channel Hubs.
• 1.0625/2.125 Gbit/s Backplanes.
• Gigabit Ethernet Retimer.

 

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PM8611 [SBSLITE™ Telecom Standard Product Data Sheet Preliminary ]

other parts : PM8611-BIAP 

PMC-Sierra
PMC-Sierra

Features
• The PM8611 SBI336 Bus Serializer (SBSLITE™) is a:
   ° Scalable Bandwidth Interconnect (SBI™) converter and Time Division Multiplexer (TDM) SBI switch.
   ° Byte-wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
   ° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S switch. Supports subrate link switching with the restriction that subrate links must be symmetric in both the transmit and receive directions.
   ° Byte-wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. This requires the TelecomBus J1 byte to be in a fixed location corresponding to a value of 0 or 522 which is immediately following the C1 octets:
   ° VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch.
• Can be used with the Narrowband Switch Elements, NSE-20G, to implement a DS0 granularity SBI Memory:Space:Memory switch scalable to 20 Gbit/s and NSE-8G, to implement a switch scalable to 8 Gbit/s. In TelecomBus mode, a 20 Gbit/s VT1.5/VT2 granularity Memory:Space:Memory switch can be implemented.
• Integrates two independent DS0 granularity Memory Switches. One switch is placed between the incoming 77.76 MHz byte-wide SBI336 bus and the transmit working and protect Serial SBI336S link. The transmit working and protect links transmit the same data. The other switch is placed between the receive working or protect Serial SBI336S link and the outgoing 77.76 MHz byte-wide SBI336 bus.
• Provides 125 µS nominal latency in DS0 mode. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multiframe (6 mS) or two E1 multiframe (4 mS).
• Provides less than 16 µS nominal latency in TelecomBus mode or SBI mode without DS0 level switching.
• Permits any receive or incoming byte from an input port to be mapped to any outgoing or transmit byte, respectively, on the associated output port through the Memory switch.
• Supports redundant working and protect serial SBI336S links in support of a redundant Memory:Space:Memory switch with the NSE.
• Encodes and decodes byte-wide SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.
• Encodes data from the Incoming SBI336 bus or TelecomBus stream to a working and protect 777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
• Decodes data from a working and protect 777.6 MHz low voltage differential serializer (LVDS) serial links with 8B/10B-based encoding to the Outgoing SBI336 bus or TelecomBus stream.
• In SBI mode, switches CAS bits with all DS0 data.
• Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.
• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.
• Provides PRBS detection for each incoming LVDS serial link for off-line link verification. PRBS is verified with STS-1 granularity.
• Provides pins to coordinate updating of the connection map of the memory switch blocks in the local device, peer SBSLITE devices and companion NSE switch device.
• Can communicate with the NSE switch device over an in-band communications channel in the LVDS links. This channel includes mechanisms for central control and configuration.
• Derives all internal timing from a single 77.76 MHz system clock to a system frame pulse.
• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 160 ball 15 mm x 15 mm PBGA.
• Consumes low power at 1.4 W.

Applications
• T1/E1 SONET/SDH Cross-connects
• T1/E1 SONET/SDH Add-Drop Multiplexers
• OC-48 Multiservice Access Multiplexers
• Channelized OC-12/OC-48 Any Service Any Port Switches
• Serial Backplane Board Interconnect
• Shelf to Shelf Cabled Serial Interconnect
• Voice Gateways

 

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PM8315 [4-Channel 1.0-1.25 Gbps Transceiver ]

other parts : PM8315-PI 

PMC-Sierra
PMC-Sierra

FEATURES
• Integrates 28 T1 framers, 21 E1 framers, a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.
• Seven T1 modes of operation:
   • Up to 28 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries into a STS-1 SPE or TU-11 tributary units into a STM-1/VC3 or TU-11 tributary units into a TUG3 in a STM-1/VC4.
   • Single STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mapper with ingress or egress per tributary link monitoring.
   • Up to 28 T1 streams M13 multiplexed into a serial DS3.
   • Up to 28 T1 streams M13 multiplexed into a DS3, the DS3 is asynchronously mapped into a STS-1 SPE.
   • DS3 M13 Multiplexer with ingress or egress per link monitoring.
   • Up to 28 DS3 multiplexed T1 streams are mapped as bit asynchronous VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing (“transmux”) function between DS3 and SONET/SDH.
   • Up to 21 T1 streams mapped as bit asynchronous TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
• Three E1 modes of operation:
   • Up to 21 E1 streams mapped as bit asynchronous VT2 virtual tributaries into a STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
   • Single STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mapper with ingress or egress per tributary link monitoring.
   • Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data or HMVIP system interfaces.
• Provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link.
• Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
• Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks.
• Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1.
• Line side interface is either from the DS3 interface via the M13 multiplex or from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
• Frames in the presence of and detects the “Japanese Yellow” alarm.

Each one of 21 E1 receiver sections:
• Provides external access for up to two de-jittered recovered T1 clocks.
• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications.
• Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link.
• Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233.
• V5.2 link indication signal detection.
• Provides a digital phase locked loop for generation of a low jitter transmit clock.
• Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
• Automatically generates and transmits DS-1 performance report messages to ANSI T1.231and ANSI T1.408 specifications.
• Supports the alternate ESF CRC-6 calculation for Japanese applications.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
• Line side interface is through either DS3 Interface via the M13 multiplex or the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper.
• System side interface is either serial clock and data, MVIP or SBI bus.

APPLICATIONS
• High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• Frame Relay switches and access devices (FRADS)
• SONET/SDH Add Drop Multiplexers
• SONET/SDH Terminal Multiplexers
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• Channelized and Unchannelized DS3 Frame Relay Interfaces

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PM8379 [20-Port 4.25 Gbit/s FC-AL Cut-Through Switch ] PMC-Sierra
PMC-Sierra

The CTS 20x4G is designed to interface directly to Fibre Channel disk drives in a storage array. It can interface directly to optics or to cables at the ingress/egress point of an enclosure and is able to determine if an incoming frame is destined for a drive within that enclosure. After determining which port is associated with the frames recipient, a cut through operation to that port is performed thereby significantly reducing system latency and improving performance.
The CTS 20x4G provides unique disk isolation features that significantly increase total system availability, reliability, and serviceability.

FEATURES
GENERAL
• 20 independent rate selectable 1.0625, 2.125 or 4.25 Gbit/s physical interfaces.
• Register and software compatible to the PM8368 PBC 18x2G, PM8369 PBC 18x4G, PM8372 PBC 4x2G and PM8377 PBC 4x4G.
• Compliant to FC jitter specifications on a per-port basis.
• Supports single-ended or differential 106.25 MHz reference clock.
• Per port monitoring and diagnostics:
• LPSM Monitoring on each port.
• Disk isolation and per port serial loopback.
• Configurable Digital Loss of Link: analog LOS Detect, 8B/10B disparity errors/error rate, CRC errors/error rate, word synchronization error/error rate, and compliant frequency of comma patterns detected (configurable thresholds for each with corresponding pin interrupts).

CUT-THROUGH SWITCHING
• Integrated cut-through switching and arbitration management enables up to 200% improvement in EDR and IOPS.
• Parallel arbitration supported with arbitration priority and access fairness preserved.
• Automatic or CPU controlled initialization of AL_PA table.
• Supports dynamic half duplex, half/full duplex operation, LPSM transfer state, multicast/broadcast (OPNy).

APPLICATIONS
• SBOD Storage Systems.
• MBOD Storage Systems.
• RAID Storage Systems.
• JBOD Storage Systems.
• FC to SATA Storage Systems.
• FC-AL Nodes.
• Fibre Channel Hubs.
• 1.0625, 2.125, and 4.25 Gbit/s Backplanes.

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PM8172 [PM8172 System Controller ] PMC-Sierra
PMC-Sierra

FEATURES
The PM8172 system controller is ideal for various designs of advanced set-top boxes, DVD players, game stations, and Internet terminal appliances. The PM8172 interfaces to PMC-Sierra’s RM5231A, RM7035C and RM7935 MIPS RISC processors.

CPU INTERFACE
• Connects to PMC-Sierra’s RM5231A, RM7035C, and RM7935 64-bit MIPS RISC microprocessors.
• Supports CPU bus frequencies up to 100 MHz.

SDRAM CONTROLLER
• 32-bit data bus interface.
• Supports two banks of SDRAM, up to 128 Mbytes in size.
• Provides a deep buffer for CPU to SDRAM burst transfers and for PCI to SDRAM burst transfers.
• Supports bus frequencies up to 100 MHz.

FLASH/ROM INTERFACE
• Supports Flash memory area up to 64 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a ROM area size up to 4 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a maximum of 12 chip-select signals.
• Shared with a 68K-like peripheral bus.

PERIPHERAL BUS CONTROLLER
• Provides a 68K-like bus interface.
• Does not require an external latch for addressing.
• Provides an 8-bit and 16-bit data bus interface.
• Shared with the Flash/ROM interface.
• Supports up to four DMA channels.
• Provides cycle posting to avoid performance hits from slower devices.

PCI BUS CONTROLLER
• Provides CPU to PCI buffers for burst
transfers.

• Provides a PCI arbiter that supports up
to five individual bus master devices.
• Supports 33 MHz bus frequency.
• Provides a 32-bit data bus interface.

INTERRUPT CONTROLLER
• Supports a maskable interrupt to the CPU and a non-maskable interrupt to the CPU for severe events.
• The priority order of interrupt request lines can be assigned by software.
• Module interrupts can be masked on/off independently by setting the corresponding mask registers.

DMA CONTROLLER
• Supports four channel requests for LPC or ECP DMA mode data transfers.
• Supports PCI bus master accessing to the SDRAM.

CHAINING DMA CONTROLLER
• Supports four independent software DMA channels for transferring data between SDRAM and PCI devices.
• Supports chaining and non-chaining modes.
• Supports rotating and fixed priority types. (Continue..)

 

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