Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site


PM8

  

数据手册 ( 数据表 )

如同 PM8
开始 PM80* PM81* PM83* PM86* PM89*
结尾 *FPM8 *SPM8 *VPM8 *3PM8 *OPM8 *JPM8 *RPM8 *MPM8 *EPM8 *DPM8 *IPM8
包括 *PM80* *PM8T*
查看详情    
PM8 [Axial Leaded Hermetically Sealed Standard Recovery Rectifier Diode ]

other parts : PM0  PM6 

Semtech
Semtech Corporation

Description
Quick reference data
  VR = 600V - 1000V
  IF = 2.0A
  trr = 3µS
  IR = 1.0µA
 
Features
♦ Avalanche capability
♦ High thermal shock resistance
♦ Glass passivated for hermetic sealing
♦ Low reverse leakage currents
♦ Low forward voltage drop

 

View
PM8172 [PM8172 System Controller ] PMC-Sierra
PMC-Sierra

FEATURES
The PM8172 system controller is ideal for various designs of advanced set-top boxes, DVD players, game stations, and Internet terminal appliances. The PM8172 interfaces to PMC-Sierra’s RM5231A, RM7035C and RM7935 MIPS RISC processors.

CPU INTERFACE
• Connects to PMC-Sierra’s RM5231A, RM7035C, and RM7935 64-bit MIPS RISC microprocessors.
• Supports CPU bus frequencies up to 100 MHz.

SDRAM CONTROLLER
• 32-bit data bus interface.
• Supports two banks of SDRAM, up to 128 Mbytes in size.
• Provides a deep buffer for CPU to SDRAM burst transfers and for PCI to SDRAM burst transfers.
• Supports bus frequencies up to 100 MHz.

FLASH/ROM INTERFACE
• Supports Flash memory area up to 64 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a ROM area size up to 4 Mbytes, with 8-bit, 16-bit, and 32-bit data access capability.
• Supports a maximum of 12 chip-select signals.
• Shared with a 68K-like peripheral bus.

PERIPHERAL BUS CONTROLLER
• Provides a 68K-like bus interface.
• Does not require an external latch for addressing.
• Provides an 8-bit and 16-bit data bus interface.
• Shared with the Flash/ROM interface.
• Supports up to four DMA channels.
• Provides cycle posting to avoid performance hits from slower devices.

PCI BUS CONTROLLER
• Provides CPU to PCI buffers for burst
transfers.

• Provides a PCI arbiter that supports up
to five individual bus master devices.
• Supports 33 MHz bus frequency.
• Provides a 32-bit data bus interface.

INTERRUPT CONTROLLER
• Supports a maskable interrupt to the CPU and a non-maskable interrupt to the CPU for severe events.
• The priority order of interrupt request lines can be assigned by software.
• Module interrupts can be masked on/off independently by setting the corresponding mask registers.

DMA CONTROLLER
• Supports four channel requests for LPC or ECP DMA mode data transfers.
• Supports PCI bus master accessing to the SDRAM.

CHAINING DMA CONTROLLER
• Supports four independent software DMA channels for transferring data between SDRAM and PCI devices.
• Supports chaining and non-chaining modes.
• Supports rotating and fixed priority types. (Continue..)

 

View
PM8310 [High Density T1/E1 Framer, VT/TU Mapper & M13 Mux with Integrated SONET/SDH Framers ]

other parts : PM8310TEMUX336 

PMC-Sierra
PMC-Sierra

PRODUCT OVERVIEW
The PM8310 TEMUX 336 is a high density T1/E1, DS3/E3 framer, VT/TU mapper, and M13 multiplexer with integrated SONET/SDH framers for OC-12/STM-4 and 4xOC-3/STM-1 applications. Feature integration and scalability make the TEMUX 336 ideal for use in ATCA/AMC line cards, voice and media gateways, routers, and multi-service and edge aggre gation switches.

PRODUCT HIGHLIGHTS
• 8 OC-3/STM-1 or 2 OC-12/STM-4 SONET/SDH framers
• 336 T1/252 E1 framers
• 12 M13 multiplexers, including support for G.747 multiplexing
• 12 DS3/E3 framers
• High order path processor for a SONET STS-12 or an SDH STM-4
• Tributary path processor for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Byte-synchronous and bit-asynchronous mapper for 336 VT1.5/TU-11s or 252 VT2/TU-12s
• Tributary path processor for 12 TU-3s
• Mapper for 12 DS3s or 12 E3s (TU-3 and AU-3)

APPLICATIONS
• ATCA/AMC-based line cards
• Voice and media gateways
• Wireless base station controllers (BSC) and radio network controllers (RNC)
• Routers and multi-service switches
• Edge aggregation switches
• Multi-service provisioning platforms

View
PM8311 [High Density T1/E1 Framer, VT/TU Mapper & M13 Mux with Integrated SONET/SDH Framers ]

other parts : PM8311TEMUX168 

PMC-Sierra
PMC-Sierra

PRODUCT OVERVIEW
The PM8311 TEMUX 168 is a single device integrating 2xOC-3/STM-1 SONET/SDH framers for working and protect links, 168/126 T1/E1 framers, 6 DS3/E3 framers, 6 M13/G.747 multiplexers and 6 VT/TU mappers.

PRODUCT HIGHLIGHTS
• 4 OC-3/STM-1 SONET/SDH framers
• 168 T1/126 E1 framers
• 6 M13 multiplexers, including support for G.747 multiplexing
• 6 DS3/E3 framers
• High order path processor for a SONET STS-3 or an SDH STM-1
• Tributary path processor for 168 VT1.5/TU-11s or 126 VT2/TU-12s
• Byte synchronous and bit asynchronous mapper for 168 VT1.5/TU-11s or 126 VT2/TU-12s
• Tributary path processor for 6 TU-3s
• Mapper for 6 DS3s or 6 E3s (TU-3 and AU-3)

INTERFACES
• Up to 4 SONET/SDH network interfaces
• SONET/SDH Transport and Path overhead interface
• Two 622-Mbit/s Extended Serial SONET/SDH Interfaces (ESSIs)
• Line-side serial interface for up to 6 DS3s or E3s
• System-side Scalable Bandwidth Interconnect (SBI) bus for high density interconnection of up to 168 T1 streams, 126 E1 streams, 6 DS3 streams, 6 E3 streams, or 6 arbitrary rate streams
• System-side serial interface for up to 6 DS3s or E3s
• Flexible bandwidth interface for up to 6 arbitrary rate ports
• 32 Mbit/s Synchronous TDM Interface (based on H-MVIP)
• Microprocessor- and IEEE 1149.1-compliant JTAG interface

PACKAGE
• 896-pin FCBGA (31 x 31 mm)
• Supports industrial temperature range (-40 ºC to 85 °C)

APPLICATIONS
• ATCA/AMC-based line cards
• Voice and media gateways
• Wireless base station controllers (BSC) and radio network controllers (RNC)
• Routers and multi-service switches
• Edge aggregation switches
• Multi-service provisioning platforms

 

View
PM8312 [High-Density 32-Channel T1/E1/J1 Framer with Integrated VT/TU Mapper & M13 Multiplexer ]

other parts : PM8312TEMUX32 

PMC-Sierra
PMC-Sierra

PRODUCT OVERVIEW
The PM8312 TEMUX 32 device is a 64-Mbit/s multi-channel T1/E1 framer with an integrated VT/TU Mapper and M13 Multiplexer.

PRODUCT HIGHLIGHTS
• This monolithic device integrates:
• 32 T1 framers.
• 32 E1 framers.
• One SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mapper.
• One full-featured M13 multiplexer with DS3 framer.
• One SONET/SDH DS3 mapper for terminating unchannelized DS-3 or DS3-multiplexed T1/E1 streams.
• Supports a wide range of T1, E1 and J1 framing formats.
• Supports DS3 framing modes such as M23, C-bit parity, and ITU-T Recommendation G.747.
• Stand-alone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload.
• Flexible line-side and system-side interface support:
   • Supports a 19.44-MHz Scaleable Bandwidth Interconnect (SBI™) Interface for high-density line-side device interconnection to PMC-Sierra's T1/E1 line interface products, including the 8-port PM4323 OCTLIU LT and the 32-port PM4329 HDLIU.
   • Provides a 19.44 or 77.76 MHz SONET/SDH Add/Drop Telecom bus interface for seamless connection with PMC-Sierra’s SONET/SDH devices.
   • Supports a byte-serial Scaleable Bandwidth Interconnect (SBI) interface at 19.44 MHz or 77.76 MHz for high-density system side device interconnection to PMC-Sierra’s link layer products.
   • Supports 8 Mbit/s H-MVIP system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1/E1 CAS channels, and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
   • Supports 28 T1 or 21 E1 links in DS3 mode and up to 32 T1 or E1 links when using the line-side SBI interface or SONET/SDH mode.
   • Supports transparent virtual tributaries when the SBI interface is used with a SONET/SDH mapper.
   • Supports insertion and extraction of arbitrary rate (e.g. fractional DS3) data streams to and from the SBI bus interface.
• Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
• Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
• Provides per-link diagnostic and line loopbacks.
• Provides PRBS generators and detectors at DS3 and E3 rates, and on each tributary for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T O.151, 0.152.
• Provides a generic eight-bit microprocessor bus interface for configuration, control and status monitoring.
• Provides a standard five-signal P1149.1 JTAG test port for boundary scan board test purposes.
• Feature-rich functional software drivers available with device.

APPLICATIONS
• Wireless Base Station Controllers or Radio Network Controllers
• Wireless Base Stations or 3G Node Bs
• Voice and Media Gateways
• Access and Edge Routers
• Multi-Service Switches
• Mult-Service Edge Aggregation Equipment
• Multi-Service Provisioning Platforms
• xDSL and FTTx Uplink Cards

 

View
PM8313 [M13 MULTIPLEXER ]

other parts : PM8313-RI  PM8313D3MX 

PMC-Sierra
PMC-Sierra

FEATURES
• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.

Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.

APPLICATIONS
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format

 

View
PM8313 [M13 MULTIPLEXER ]

other parts : PM8313-RI  PM8313D3MX 

PMC
PMC-Sierra, Inc

FEATURES
• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.

Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.

APPLICATIONS
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format

 

View
PM8315 [4-Channel 1.0-1.25 Gbps Transceiver ]

other parts : PM8315-PI 

PMC-Sierra
PMC-Sierra

FEATURES
• Integrates 28 T1 framers, 21 E1 framers, a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.
• Seven T1 modes of operation:
   • Up to 28 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries into a STS-1 SPE or TU-11 tributary units into a STM-1/VC3 or TU-11 tributary units into a TUG3 in a STM-1/VC4.
   • Single STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mapper with ingress or egress per tributary link monitoring.
   • Up to 28 T1 streams M13 multiplexed into a serial DS3.
   • Up to 28 T1 streams M13 multiplexed into a DS3, the DS3 is asynchronously mapped into a STS-1 SPE.
   • DS3 M13 Multiplexer with ingress or egress per link monitoring.
   • Up to 28 DS3 multiplexed T1 streams are mapped as bit asynchronous VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing (“transmux”) function between DS3 and SONET/SDH.
   • Up to 21 T1 streams mapped as bit asynchronous TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
• Three E1 modes of operation:
   • Up to 21 E1 streams mapped as bit asynchronous VT2 virtual tributaries into a STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
   • Single STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mapper with ingress or egress per tributary link monitoring.
   • Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data or HMVIP system interfaces.
• Provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link.
• Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
• Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks.
• Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1.
• Line side interface is either from the DS3 interface via the M13 multiplex or from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
• Frames in the presence of and detects the “Japanese Yellow” alarm.

Each one of 21 E1 receiver sections:
• Provides external access for up to two de-jittered recovered T1 clocks.
• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications.
• Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link.
• Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233.
• V5.2 link indication signal detection.
• Provides a digital phase locked loop for generation of a low jitter transmit clock.
• Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
• Automatically generates and transmits DS-1 performance report messages to ANSI T1.231and ANSI T1.408 specifications.
• Supports the alternate ESF CRC-6 calculation for Japanese applications.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
• Line side interface is through either DS3 Interface via the M13 multiplex or the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper.
• System side interface is either serial clock and data, MVIP or SBI bus.

APPLICATIONS
• High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• Frame Relay switches and access devices (FRADS)
• SONET/SDH Add Drop Multiplexers
• SONET/SDH Terminal Multiplexers
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• Channelized and Unchannelized DS3 Frame Relay Interfaces

View
PM8316 [High Density 84-Channel T1/E1/J1 Framer with Integrated VT/TU Mappers and M13 ] PMC-Sierra
PMC-Sierra

FEATURES
The PM8316 TEMUX-84 is a 155 Mbit/s multi-channel T1/E1 Framer with integrated VT/TU Mappers and M13 Multiplexers.
• This monolithic device integrates:
   • 84 T1 framers
   • 63 E1 framers
   • Three SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mappers
   • Three full featured M13 multiplexers with DS3 framers
   • Three SONET/SDH DS3 mappers for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams
• Each SPE/STS-1 can be independently programmed for various T1, E1 or DS3 modes of operation.
• Supports wide range of T1, E1 and J1 framing formats.
• Supports M23 and C-bit parity DS3 formats.
• Stand-alone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload.
• Flexible line side and system side interface support :
   • Provides a 19.44 or 77.76 MHz SONET/SDH Add/Drop Telecom bus interface for seamless connection with PMC’s SONET/SDH devices.
   • Supports a byte serial Scaleable Bandwidth Interconnect (SBI™) bus interface at either 19.44 MHz or 77.76 MHz for high density system side device interconnection to PMC’s link layer products.
   • Supports 8 Mbit/s H-MVIP on the system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
   • Support for transparent virtual tributaries when SBI interface is used with SONET/SDH mapper.
   • Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to/from the SBI bus interface.
• Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
• Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
• Provides per link diagnostic and line loopbacks.
• Provides PRBS generators and detectors at DS3 and E3 rates and on each tributary for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T O.151, 0.152.
• Feature-rich functional software drivers available with device.
• Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

APPLICATIONS
• High density T1/E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
• Channelized and Unchannelized DS3 Frame Relay Interfaces.
• Optical Access Equipment
• SONET/SDH Add Drop and Terminal Multiplexers.
• M13 Multiplexer/Demultiplexer Equipment.
• Digital Access Cross-Connect Systems

View
PM8351 [8-Channel 1.0-1.25 Gbps Transceiver ] PMC-Sierra
PMC-Sierra

GENERAL DESCRIPTION
The OctalPHYTM is an octal PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links. It provides eight individual serial channels capable of operation at up to 1.25 Gbps, which may be grouped together to form a single 12.5 Gbps bidirectional link.
The OctalPHY includes 8B/10B block coding logic (compliant with 802.3z Gigabit Ethernet and FibreChannel requirements) which produces run length limited data streams for serial transmission.

FEATURES
• Eight independent 1.0-1.25 Gbit/s transceivers
• Ultra low power operation: 1.25 Watts typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Optional receive FIFO which synchronizes incoming data to local clock domain
• Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• “Trunking” feature to de-skew and align received parallel data across eight channels
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 FibreChannel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5 V, 0.25 µ CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGA

APPLICATIONS
• High speed serial backplanes
• Gigabit Ethernet links
• FibreChannel links
• Intra-system interconnect
• ASIC to PMD link

 

View
1 2 3 4 5
Share Link : 

HOME




Language : English   한국어     日本語     русский     español
@ 2015 - 2018  [ Home ][ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]