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开始 PM8* PM80* PM81* PM83* PM86* PM89*
结尾 *3PM8 *FPM8 *SPM8 *VPM8
包括 *OPM8* *JPM8* *RPM8* *MPM8* *EPM8* *DPM8* *IPM8*


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PM8 Axial Leaded Hermetically Sealed Standard Recovery Rectifier Diode

Quick reference data
  VR = 600V - 1000V
  IF = 2.0A
  trr = 3µS
  IR = 1.0µA
♦ Avalanche capability
♦ High thermal shock resistance
♦ Glass passivated for hermetic sealing
♦ Low reverse leakage currents
♦ Low forward voltage drop


other parts : PM0 PM6 
PM8372 4-Port FC/GE Retimer and FC-AL Port Bypass Controller

• Supports 4 Fibre Channel Physical Interfaces at 1.0625 or 2.125 Gbit/s per Fibre Channel – Physical Interface (FC-PI) or 4 Gigabit Ethernet Retimers at 1.25 Gbit/s per IEEE 802.3z.
• Each port supports FC 1G or 2G rate detection/auto-selection.
• Supports Arbitrated Loop and Retimer configuration.
• Each port is independently selectable to perform retimer, reclocker or bypass-path function.
• Non-blocking crossconnect supports protection switching, broadcasting and multicasting.
• Automatic selection of retimer, reclocker or bypass-path function to minimize latency and jitter when a disk is bypassed.
• Per-port receive monitoring for loss of signal, error rate, and link level violations.
• Supports single-ended or differential 106.25 MHz reference clock REFCLK for Fibre Channel applications or 125 Mhz reference clock for Gigabit Ethernet applications.

• High-speed outputs with selectable preemphasis per port to counteract dielectric losses and allow maximum reach on printed circuit boards.
• Selectable receive input equalization for improved signal integrity.
• Minimized board footprint and improved signal integrity achieved because:
   • No external components are required to interface the high-speed signals to optics, coax, or serial backplanes using the internal AC coupling capacitors and terminating resistors.
   • Receive input termination of 100 Ω or 150 Ω differential is selectable.
   • Source output impedance of 100 Ω or 150 Ω differential is programmable.
• FC-AL Nodes.
• RAID Storage Systems.
• JBOD Storage Systems.
• MBOD Storage Systems.
• SBOD Storage Systems.
• Fibre Channel Hubs.
• 1.0625/2.125 Gbit/s Backplanes.
• Gigabit Ethernet Retimer.



• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
• • Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.

Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.

Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.

• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format


other parts : PM8313-RI PM8313D3MX 
PM8621 8G Narrowband Switch Element

The PM8621 NSE-8G is a monolithic CMOS integrated circuit packaged in a 480 ball UBGA that performs DS0 and above granularity space switching on 12 SBI336 streams carried as serial SBI336S in 8B/10B coding over LVDS at 777.6 Mbit/s. The NSE-8G also performs VT1.5/VT2 and above granularity switching on 12 STS-12/STM-4 SONET/SDH streams, carried as Serial TelecomBus signals in 8B/10B coding over LVDS at 777.6 Mbit/s.

other parts : PM8621-BIAP 
PM8312 High-Density 32-Channel T1/E1/J1 Framer with Integrated VT/TU Mapper & M13 Multiplexer

The PM8312 TEMUX 32 device is a 64-Mbit/s multi-channel T1/E1 framer with an integrated VT/TU Mapper and M13 Multiplexer.

• This monolithic device integrates:
• 32 T1 framers.
• 32 E1 framers.
• One SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous or byte synchronous mapper.
• One full-featured M13 multiplexer with DS3 framer.
• One SONET/SDH DS3 mapper for terminating unchannelized DS-3 or DS3-multiplexed T1/E1 streams.
• Supports a wide range of T1, E1 and J1 framing formats.
• Supports DS3 framing modes such as M23, C-bit parity, and ITU-T Recommendation G.747.
• Stand-alone unchannelized E3 framer mode (ITU-T Rec. G.751 or G.832) for access to the entire E3 payload.
• Flexible line-side and system-side interface support:
   • Supports a 19.44-MHz Scaleable Bandwidth Interconnect (SBI™) Interface for high-density line-side device interconnection to PMC-Sierra's T1/E1 line interface products, including the 8-port PM4323 OCTLIU LT and the 32-port PM4329 HDLIU.
   • Provides a 19.44 or 77.76 MHz SONET/SDH Add/Drop Telecom bus interface for seamless connection with PMC-Sierra’s SONET/SDH devices.
   • Supports a byte-serial Scaleable Bandwidth Interconnect (SBI) interface at 19.44 MHz or 77.76 MHz for high-density system side device interconnection to PMC-Sierra’s link layer products.
   • Supports 8 Mbit/s H-MVIP system interface for all T1 or E1 links, a separate 8 Mbit/s H-MVIP system interface for all T1/E1 CAS channels, and a separate 8 Mbit/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
   • Supports 28 T1 or 21 E1 links in DS3 mode and up to 32 T1 or E1 links when using the line-side SBI interface or SONET/SDH mode.
   • Supports transparent virtual tributaries when the SBI interface is used with a SONET/SDH mapper.
   • Supports insertion and extraction of arbitrary rate (e.g. fractional DS3) data streams to and from the SBI bus interface.
• Provides jitter attenuation in the T1/E1 tributary receive and transmit directions.
• Provides three independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
• Provides per-link diagnostic and line loopbacks.
• Provides PRBS generators and detectors at DS3 and E3 rates, and on each tributary for error testing at T1, E1 and NxDS0 rates as recommended in ITU-T O.151, 0.152.
• Provides a generic eight-bit microprocessor bus interface for configuration, control and status monitoring.
• Provides a standard five-signal P1149.1 JTAG test port for boundary scan board test purposes.
• Feature-rich functional software drivers available with device.

• Wireless Base Station Controllers or Radio Network Controllers
• Wireless Base Stations or 3G Node Bs
• Voice and Media Gateways
• Access and Edge Routers
• Multi-Service Switches
• Mult-Service Edge Aggregation Equipment
• Multi-Service Provisioning Platforms
• xDSL and FTTx Uplink Cards


other parts : PM8312TEMUX32 
PM8351 8-Channel 1.0-1.25 Gbps Transceiver

The OctalPHYTM is an octal PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links. It provides eight individual serial channels capable of operation at up to 1.25 Gbps, which may be grouped together to form a single 12.5 Gbps bidirectional link.
The OctalPHY includes 8B/10B block coding logic (compliant with 802.3z Gigabit Ethernet and FibreChannel requirements) which produces run length limited data streams for

PM8611 SBSLITE™ Telecom Standard Product Data Sheet Preliminary

• The PM8611 SBI336 Bus Serializer (SBSLITE™) is a:
   ° Scalable Bandwidth Interconnect (SBI™) converter and Time Division Multiplexer (TDM) SBI switch.
   ° Byte-wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
   ° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S switch. Supports subrate link switching with the restriction that subrate links must be symmetric in both the transmit and receive directions.
   ° Byte-wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. This requires the TelecomBus J1 byte to be in a fixed location corresponding to a value of 0 or 522 which is immediately following the C1 octets:
   ° VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch.
• Can be used with the Narrowband Switch Elements, NSE-20G, to implement a DS0 granularity SBI Memory:Space:Memory switch scalable to 20 Gbit/s and NSE-8G, to implement a switch scalable to 8 Gbit/s. In TelecomBus mode, a 20 Gbit/s VT1.5/VT2 granularity Memory:Space:Memory switch can be implemented.
• Integrates two independent DS0 granularity Memory Switches. One switch is placed between the incoming 77.76 MHz byte-wide SBI336 bus and the transmit working and protect Serial SBI336S link. The transmit working and protect links transmit the same data. The other switch is placed between the receive working or protect Serial SBI336S link and the outgoing 77.76 MHz byte-wide SBI336 bus.
• Provides 125 µS nominal latency in DS0 mode. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multiframe (6 mS) or two E1 multiframe (4 mS).
• Provides less than 16 µS nominal latency in TelecomBus mode or SBI mode without DS0 level switching.
• Permits any receive or incoming byte from an input port to be mapped to any outgoing or transmit byte, respectively, on the associated output port through the Memory switch.
• Supports redundant working and protect serial SBI336S links in support of a redundant Memory:Space:Memory switch with the NSE.
• Encodes and decodes byte-wide SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.
• Encodes data from the Incoming SBI336 bus or TelecomBus stream to a working and protect 777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
• Decodes data from a working and protect 777.6 MHz low voltage differential serializer (LVDS) serial links with 8B/10B-based encoding to the Outgoing SBI336 bus or TelecomBus stream.
• In SBI mode, switches CAS bits with all DS0 data.
• Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.
• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.
• Provides PRBS detection for each incoming LVDS serial link for off-line link verification. PRBS is verified with STS-1 granularity.
• Provides pins to coordinate updating of the connection map of the memory switch blocks in the local device, peer SBSLITE devices and companion NSE switch device.
• Can communicate with the NSE switch device over an in-band communications channel in the LVDS links. This channel includes mechanisms for central control and configuration.
• Derives all internal timing from a single 77.76 MHz system clock to a system frame pulse.
• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 160 ball 15 mm x 15 mm PBGA.
• Consumes low power at 1.4 W.

• T1/E1 SONET/SDH Cross-connects
• T1/E1 SONET/SDH Add-Drop Multiplexers
• OC-48 Multiservice Access Multiplexers
• Channelized OC-12/OC-48 Any Service Any Port Switches
• Serial Backplane Board Interconnect
• Shelf to Shelf Cabled Serial Interconnect
• Voice Gateways


other parts : PM8611-BIAP 
PM8610 SBI Bus Serializer (SBS)

The PM8610 SBI336 Bus Serializer (SBS) is a monolithic integrated circuit that implements conversion between a byte-serial 19.44 MHz SBI bus or 77.76 MHz SBI336 bus and a redundant
777.6 Mbit/s bit-serial 8B/10B-base SBI336S bus.
In TelecomBus mode, the SBS implements conversion between any 19.44 MHz TelecomBus or
77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial
TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input
DS0 to be output on any output DS0. The redundant 777.6 Mbit/s serial interfaces can be disabled
and a byte-wide SBI336 bus can be enabled in its place with all the DS0 level switching


other parts : PM8610-BIAP 
PM8379 20-Port 4.25 Gbit/s FC-AL Cut-Through Switch

The CTS 20x4G is designed to interface directly to Fibre Channel disk drives in a storage array. It can interface directly to optics or to cables at the ingress/egress point of an enclosure and is able to determine if an incoming frame is destined for a drive within that enclosure. After determining which port is associated with the frames recipient, a cut through operation to that port is performed thereby significantly reducing system latency and improving performance.
The CTS 20x4G provides unique disk isolation features that significantly increase total system availability, reliability, and serviceability.

• 20 independent rate selectable 1.0625, 2.125 or 4.25 Gbit/s physical interfaces.
• Register and software compatible to the PM8368 PBC 18x2G, PM8369 PBC 18x4G, PM8372 PBC 4x2G and PM8377 PBC 4x4G.
• Compliant to FC jitter specifications on a per-port basis.
• Supports single-ended or differential 106.25 MHz reference clock.
• Per port monitoring and diagnostics:
• LPSM Monitoring on each port.
• Disk isolation and per port serial loopback.
• Configurable Digital Loss of Link: analog LOS Detect, 8B/10B disparity errors/error rate, CRC errors/error rate, word synchronization error/error rate, and compliant frequency of comma patterns detected (configurable thresholds for each with corresponding pin interrupts).

• Integrated cut-through switching and arbitration management enables up to 200% improvement in EDR and IOPS.
• Parallel arbitration supported with arbitration priority and access fairness preserved.
• Automatic or CPU controlled initialization of AL_PA table.
• Supports dynamic half duplex, half/full duplex operation, LPSM transfer state, multicast/broadcast (OPNy).

• SBOD Storage Systems.
• MBOD Storage Systems.
• RAID Storage Systems.
• JBOD Storage Systems.
• FC to SATA Storage Systems.
• FC-AL Nodes.
• Fibre Channel Hubs.
• 1.0625, 2.125, and 4.25 Gbit/s Backplanes.

PM8355 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support

The QuadPHY-II is a physical layer transceiver ideal for systems requiring high speed point-to-point communication links. It is applicable for PMAPMD connections in 10 GE, Infiniband 1 or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s Fibre Channel, as well as high speed serial backplanes for high capacity systems.



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