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R5F7136

  

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R5F7136 [Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family ]

other parts : R5F7131  R5F7132  R5F7137  SH7131  SH7132  SH7136  SH7137 

Renesas
Renesas Electronics

Overview
Features of SH7131, SH7132, SH7136, and SH7137
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.
The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, a data transfer controller (DTC), timers, a serial communication interface (SCI), a synchronous serial communication unit (SSU), an A/D converter, an interrupt controller (INTC), I/O ports, I2C bus interface 2 (I2C2), and controller area network (RCAN-ET).
This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs (available only with the SH7132 and SH7137). These on-chip functions significantly reduce costs of designing and manufacturing application systems.
The version of on-chip ROM is F-ZTAT™ (Flexible Zero Turn Around Time)* that includes flash memory. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be reprogrammed at a user-site while mounted on a board.

CPU
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles
• C language-oriented 62 basic instructions

Operating modes
• Operating modes
   - Single chip mode
   - Extended ROM enabled mode (Only in SH7132/SH7137)
   - Extended ROM disabled mode (Only in SH7132/SH7137)
• Operating states
   - Program execution state
   - Exception handling state
   - Bus release state (Only in SH7132/SH7137)
• Power-down modes
   - Sleep mode
   - Software standby mode (Only in SH7136/SH7137)
   - Deep software standby mode (Only in SH7136/SH7137)
   - Module standby mode

User break controller (UBC)
• Addresses, data values, type of access, and data size can all be set as break conditions
• Supports a sequential break function
(SH7132 and SH7137 only)
• Two break channels

On-chip ROM
• 128 Kbytes (Only in SH7131/SH7132) or 256 Kbytes

On-chip RAM
• 8 Kbytes (Only in SH7131/SH7132) or 16 Kbytes

Bus state controller (BSC)
• Address space: A maximum 1 Mbyte for each of two areas (CS0 and CS1) (Only in SH7132/SH7137)
• 8-bit external bus (Only in SH7132/SH7137)
• The following features settable for each area independently
   - Number of access wait cycles
   - Idle wait cycle insertion
   - Supports SRAM
• Outputs a chip select signal according to the target area

Data transfer controller (DTC)
• Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU.
   - A CPU interrupt can be requested after one data transfer completion.
   - A CPU interrupt can be requested after all specified data transfer completion.
  
Interrupt controller (INTC)
• Five external interrupt pins (NMI and IRQ3 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source

View
R5F71364AN80FPV [Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family ]

other parts : R5F7131  R5F7132  R5F7136  R5F7137  SH7131  SH7132  SH7136 

Renesas
Renesas Electronics

Overview
Features of SH7131, SH7132, SH7136, and SH7137
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.
The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, a data transfer controller (DTC), timers, a serial communication interface (SCI), a synchronous serial communication unit (SSU), an A/D converter, an interrupt controller (INTC), I/O ports, I2C bus interface 2 (I2C2), and controller area network (RCAN-ET).
This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs (available only with the SH7132 and SH7137). These on-chip functions significantly reduce costs of designing and manufacturing application systems.
The version of on-chip ROM is F-ZTAT™ (Flexible Zero Turn Around Time)* that includes flash memory. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be reprogrammed at a user-site while mounted on a board.

CPU
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles
• C language-oriented 62 basic instructions

Operating modes
• Operating modes
   - Single chip mode
   - Extended ROM enabled mode (Only in SH7132/SH7137)
   - Extended ROM disabled mode (Only in SH7132/SH7137)
• Operating states
   - Program execution state
   - Exception handling state
   - Bus release state (Only in SH7132/SH7137)
• Power-down modes
   - Sleep mode
   - Software standby mode (Only in SH7136/SH7137)
   - Deep software standby mode (Only in SH7136/SH7137)
   - Module standby mode

User break controller (UBC)
• Addresses, data values, type of access, and data size can all be set as break conditions
• Supports a sequential break function
(SH7132 and SH7137 only)
• Two break channels

On-chip ROM
• 128 Kbytes (Only in SH7131/SH7132) or 256 Kbytes

On-chip RAM
• 8 Kbytes (Only in SH7131/SH7132) or 16 Kbytes

Bus state controller (BSC)
• Address space: A maximum 1 Mbyte for each of two areas (CS0 and CS1) (Only in SH7132/SH7137)
• 8-bit external bus (Only in SH7132/SH7137)
• The following features settable for each area independently
   - Number of access wait cycles
   - Idle wait cycle insertion
   - Supports SRAM
• Outputs a chip select signal according to the target area

Data transfer controller (DTC)
• Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU.
   - A CPU interrupt can be requested after one data transfer completion.
   - A CPU interrupt can be requested after all specified data transfer completion.
  
Interrupt controller (INTC)
• Five external interrupt pins (NMI and IRQ3 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source

View
R5F71364AD80FPV [Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family ]

other parts : R5F7131  R5F7132  R5F7136  R5F7137  SH7131  SH7132  SH7136 

Renesas
Renesas Electronics

Overview
Features of SH7131, SH7132, SH7136, and SH7137
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.
The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, a data transfer controller (DTC), timers, a serial communication interface (SCI), a synchronous serial communication unit (SSU), an A/D converter, an interrupt controller (INTC), I/O ports, I2C bus interface 2 (I2C2), and controller area network (RCAN-ET).
This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs (available only with the SH7132 and SH7137). These on-chip functions significantly reduce costs of designing and manufacturing application systems.
The version of on-chip ROM is F-ZTAT™ (Flexible Zero Turn Around Time)* that includes flash memory. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be reprogrammed at a user-site while mounted on a board.

CPU
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles
• C language-oriented 62 basic instructions

Operating modes
• Operating modes
   - Single chip mode
   - Extended ROM enabled mode (Only in SH7132/SH7137)
   - Extended ROM disabled mode (Only in SH7132/SH7137)
• Operating states
   - Program execution state
   - Exception handling state
   - Bus release state (Only in SH7132/SH7137)
• Power-down modes
   - Sleep mode
   - Software standby mode (Only in SH7136/SH7137)
   - Deep software standby mode (Only in SH7136/SH7137)
   - Module standby mode

User break controller (UBC)
• Addresses, data values, type of access, and data size can all be set as break conditions
• Supports a sequential break function
(SH7132 and SH7137 only)
• Two break channels

On-chip ROM
• 128 Kbytes (Only in SH7131/SH7132) or 256 Kbytes

On-chip RAM
• 8 Kbytes (Only in SH7131/SH7132) or 16 Kbytes

Bus state controller (BSC)
• Address space: A maximum 1 Mbyte for each of two areas (CS0 and CS1) (Only in SH7132/SH7137)
• 8-bit external bus (Only in SH7132/SH7137)
• The following features settable for each area independently
   - Number of access wait cycles
   - Idle wait cycle insertion
   - Supports SRAM
• Outputs a chip select signal according to the target area

Data transfer controller (DTC)
• Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU.
   - A CPU interrupt can be requested after one data transfer completion.
   - A CPU interrupt can be requested after all specified data transfer completion.
  
Interrupt controller (INTC)
• Five external interrupt pins (NMI and IRQ3 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source

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