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SN54LS73

  

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SN54LS73 [DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP ]

other parts : SN74LS73  SN54LS73J  SN74LS73A  SN74LS73D  SN74LS73N  SN54LS73AJ  SN74LS73AD  SN74LS73AN 

Motorola
Motorola => Freescale

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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SN54LS73A [DUAL J-K FLIP-FLOPS WITH CLEAR ]

other parts : SN5473  SN7473  SN7473N  SN5473W  SN5473J  SN7473N3  SN74LS73A  SN54LS73AW  SN54LS73AJ  SN74LS73AD 

TI
Texas Instruments

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SN54LS73A [DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY ]

other parts : 74LS73  74LS73A  SB74LS73A 

Motorola
Motorola => Freescale

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will performaccording to the truth table as long as minimum set-up times are observed.Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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SN54LS73J [DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP ]

other parts : SN54LS73  SN74LS73  SN74LS73A  SN74LS73D  SN74LS73N  SN54LS73AJ  SN74LS73AD  SN74LS73AN 

Motorola
Motorola => Freescale

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

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SN54LS73AJ [DUAL J-K FLIP-FLOPS WITH CLEAR ]

other parts : SN5473  SN7473  SN5473W  SN5473J  SN7473N  SN7473N3  SN54LS73A  SN74LS73A  SN54LS73AW  SN74LS73AD 

TI
Texas Instruments

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SN54LS73AJ [DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP ]

other parts : SN54LS73  SN74LS73  SN54LS73J  SN74LS73A  SN74LS73D  SN74LS73N  SN74LS73AD  SN74LS73AN 

Motorola
Motorola => Freescale

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

View
SN54LS73AW [DUAL J-K FLIP-FLOPS WITH CLEAR ]

other parts : SN5473  SN7473  SN7473N  SN5473W  SN5473J  SN7473N3  SN54LS73A  SN74LS73A  SN54LS73AJ  SN74LS73AD 

TI
Texas Instruments

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