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SN74LS76A

  

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SN74LS76A [DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR ]

other parts : 5962-9557501QEA  5962-9557501QFA  7601301EA  JM38510/00204BEA  M38510/00204BEA  SN5476J  SN54LS76AJ 

Texas-Instruments
Texas Instruments

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SN74LS76A [LOW POWER SCHOTTKY ]

other parts : SN74LS76  SN74LS76AD  SN74LS76ADR2  SN74LS76AN 

ON-Semiconductor
ON Semiconductor

Dual JK Flip-Flop with Set and Clear

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

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SN74LS76A [DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR ]

other parts : 5962-9557501QEA  5962-9557501QFA  7601301EA  JM38510/00204BEA  M38510/00204BEA  SN5476J  SN54LS76AJ 

TI
Texas Instruments


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SN74LS76A [DUAL JK FLIP-FLOP WITH SET AND CLEAR ]

other parts : SN54LS76A  SN54LS76AJ  SN74LS76AD  SN74LS76AN 

Motorola
Motorola => Freescale

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

View
SN74LS76AD [LOW POWER SCHOTTKY ]

other parts : SN74LS76  SN74LS76A  SN74LS76ADR2  SN74LS76AN 

ON-Semiconductor
ON Semiconductor

Dual JK Flip-Flop with Set and Clear

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

View
SN74LS76AN [LOW POWER SCHOTTKY ]

other parts : SN74LS76  SN74LS76A  SN74LS76AD  SN74LS76ADR2 

ON-Semiconductor
ON Semiconductor

Dual JK Flip-Flop with Set and Clear

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

View
SN74LS76AD [DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR ]

other parts : 5962-9557501QEA  5962-9557501QFA  7601301EA  JM38510/00204BEA  M38510/00204BEA  SN5476J  SN54LS76AJ 

TI
Texas Instruments


View
SN74LS76AD [DUAL JK FLIP-FLOP WITH SET AND CLEAR ]

other parts : SN54LS76A  SN54LS76AJ  SN74LS76A  SN74LS76AN 

Motorola
Motorola => Freescale

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

View
SN74LS76AN [DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR ]

other parts : 5962-9557501QEA  5962-9557501QFA  7601301EA  JM38510/00204BEA  M38510/00204BEA  SN5476J  SN54LS76AJ 

TI
Texas Instruments


View
SN74LS76AN [DUAL JK FLIP-FLOP WITH SET AND CLEAR ]

other parts : SN54LS76A  SN54LS76AJ  SN74LS76A  SN74LS76AD 

Motorola
Motorola => Freescale

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

 

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