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XRT79L71

  

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XRT79L71_2003 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71IB_2003 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of ATM or HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control. Industry standard UTOPIA II and POS-PHY interface are also provided.

GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
   frequency clock and generates either DS3 or E3
   frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
   Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 208 STBl PBGA Package
• JTAG Interface (Continue ...)

APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches

View
XRT79L71_2007 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71IB_2007 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of ATM or HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control. Industry standard UTOPIA II and POS-PHY interface are also provided.

GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
   frequency clock and generates either DS3 or E3
   frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
   Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 208 STBGA Package
• JTAG Interface  (Continue ...)

APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches

View
XRT79L71 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71IB  XRT79L71_10 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support Frame processing. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control.

GENERAL FEATURES:
● Integrated T3/E3 Line Interface Unit
● Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
● HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
● Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
● Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
● Supports M13 and C-Bit Parity Framing Formats
● Supports DS3/E3 Clear-Channel Framing.
● Includes PRBS Generator and Receiver
● Supports Line, Cell, and PLCP Loop-backs
● Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
● Low power 3.3V, 5V Input Tolerant, CMOS
● Available in 208 STBGA Package
● JTAG Interface (Continue ...)

APPLICATIONS
● Digital Access and Cross Connect Systems
● 3G Base Stations
● DSLAMs

View
XRT79L71IB_2003 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71_2003 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of ATM or HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control. Industry standard UTOPIA II and POS-PHY interface are also provided.

GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
   frequency clock and generates either DS3 or E3
   frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
   Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 208 STBl PBGA Package
• JTAG Interface (Continue ...)

APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches

View
XRT79L71IB_2007 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71_2007 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of ATM or HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control. Industry standard UTOPIA II and POS-PHY interface are also provided.

GENERAL FEATURES:
• Integrated T3/E3 Line Interface Unit
• Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
• Flexible integrated Clock Multiplier that takes single
   frequency clock and generates either DS3 or E3
   frequency.
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
   Interface operating at 25, 33 or 50 MHz.
• HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
• Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
• Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
• Supports ATM cell or PPP Packet Mapping
• Supports M13 and C-Bit Parity Framing Formats
• Supports DS3/E3 Clear-Channel Framing.
• Includes PRBS Generator and Receiver
• Supports Line, Cell, and PLCP Loop-backs
• Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
• Low power 3.3V, 5V Input Tolerant, CMOS
• Available in 208 STBGA Package
• JTAG Interface  (Continue ...)

APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches

View
XRT79L71IB [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71  XRT79L71_10 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support Frame processing. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control.

GENERAL FEATURES:
● Integrated T3/E3 Line Interface Unit
● Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
● HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
● Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
● Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
● Supports M13 and C-Bit Parity Framing Formats
● Supports DS3/E3 Clear-Channel Framing.
● Includes PRBS Generator and Receiver
● Supports Line, Cell, and PLCP Loop-backs
● Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
● Low power 3.3V, 5V Input Tolerant, CMOS
● Available in 208 STBGA Package
● JTAG Interface (Continue ...)

APPLICATIONS
● Digital Access and Cross Connect Systems
● 3G Base Stations
● DSLAMs

View
XRT79L71_10 [1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE ]

other parts : XRT79L71  XRT79L71IB 

Exar
Exar Corporation

GENERAL DESCRIPTION
The XRT79L71 is a single channel, integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support Frame processing. For Clear-Channel Framer applications, this device supports the transmission and reception of “user data” via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line Interface Unit with Jitter Attenuator that supports mapping of HDLC framed data. A flexible parallel microprocessor interface is provided for configuration and control.

GENERAL FEATURES:
● Integrated T3/E3 Line Interface Unit
● Integrated Jitter Attenuator that can be selected
   either in Receive or Transmit path
● HDLC Controller that provides the mapping/
   extraction of either bit or byte mapped
   encapsulated packet from DS3/E3 Frame.
● Contains on-chip 16 cell FIFO (configurable in
   depths of 4, 8, 12 or 16 cells), in both the Transmit
   (TxFIFO) and Receive Directions (RxFIFO)
● Contains on-chip 54 byte Transmit and Receive
   OAM Cell Buffer for transmission, reception and
   processing of OAM Cells
● Supports M13 and C-Bit Parity Framing Formats
● Supports DS3/E3 Clear-Channel Framing.
● Includes PRBS Generator and Receiver
● Supports Line, Cell, and PLCP Loop-backs
● Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
   and Mips µPs
● Low power 3.3V, 5V Input Tolerant, CMOS
● Available in 208 STBGA Package
● JTAG Interface (Continue ...)

APPLICATIONS
● Digital Access and Cross Connect Systems
● 3G Base Stations
● DSLAMs

View
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