Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site


8029

  

Datasheet

Match, Like 8029
Start with 80296*
End *F8029 *D8029 *N8029 *A8029 *18029 *78029 *S8029 *L8029
Included *8029-* *8029A* *8029C* *8029H* *8029S* *8029_*
View Details    
UPD78F8029 [Available microcontroller list for PG-FP5 ]

other parts : D70F3425  R5F10968  R5F1096A  R5F1096B  R5F1096C  R5F1096D  R5F1096E  R5F109AA  R5F109AB  R5F109AC 

ETC
Unspecified

[Renesas]

This is information about the next version of PG-FP5 (modules), etc.(2014/3 update)

View
AD8029 [Low Power, High Speed Rail-to-Rail Input/Output Amplifier ]

other parts : AD8030  AD8040  AD8029AR  AD8029AR-REEL  AD8029AR-REEL7  AD8029AKS-R2  AD8029AKS-REEL  AD8029AKS-REEL7  AD8030AR  AD8030AR-REEL 

ADI
Analog Devices

GENERAL DESCRIPTION
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail input and output high speed amplifiers with a quiescent current of only 1.3 mA per amplifier. Despite their low power consumption, the amplifiers provide excellent performance with 125 MHz small signal bandwidth and 60 V/µs slew rate. ADI’s proprietary XFCB process enables high speed and high performance on low power.
This family of amplifiers exhibits true single-supply operation with rail-to-rail input and output performance for supply voltages ranging from 2.7 V to 12 V. The input voltage range extends 200 mV beyond each rail without phase reversal. The dynamic range of the output extends to within 40 mV of each rail.

FEATURES
   Low power
      1.3 mA supply current/amplifier
   High speed
      125 MHz, –3 dB bandwidth (G = +1)
      60 V/µs slew rate
      80 ns settling time to 0.1%
   Rail-to-rail input and output
      No phase reversal, inputs 200 mV beyond rails
   Wide supply range: 2.7 V to 12 V
   Offset voltage: 6 mV max
   Low input bias current
      +0.7 µA to –1.5 µA
   Small packaging
      SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14

APPLICATIONS
   Battery-powered instrumentation
   Filters
   A-to-D drivers
   Buffering

View
TDA8029 [Low power single card reader ]

other parts : TDA8029C1  TDA8029C2  TDA8029HL  TDA8029HL/C1  TDA8029HL/C2 

Philips
Philips Electronics

GENERAL DESCRIPTION
The TDA8029 is a complete one chip, low cost, low power, robust smart card reader. Its different power reduction modes and its wide supply voltage range allow its use in portable equipment. Due to specific versatile hardware, a small embedded software program allows the control of most cards available in the market. The control from the host may be done through a standard serial interface.

FEATURES
• 80C51 core with 16 kbytes ROM, 256 bytes RAM and 512 bytes XRAM
• Specific ISO7816 UART, accessible with MOVX instructions for automatic convention processing, variable baud rate, error management at character level for T = 0 and T = 1 protocols, extra guard time, etc.
• Specific versatile 24-bit Elementary Time Unit (ETU) counter for timing processing during Answer To Reset (ATR) and for T = 1 protocol
• VCC generation (5 V ± 5 % or 3 V ± 5 % or 1.8 V), maximum current 65 mA with controlled rise and fall times
• Card clock generation up to 20 MHz with three times synchronous frequency doubling (fXTAL, 1/2fXTAL, 1/4fXTAL and 1/8fXTAL)
• Card clock stop HIGH or LOW or 1.25 MHz from an integrated oscillator for card power reduction modes
• Automatic activation and deactivation sequences through an independant sequencer
• Supports asynchronous protocols T = 0 and T = 1 in accordance with:
   – ISO 7816 and EMV 3.1.1 (TDA8029HL/C1 and TDA8029HL/C2)
   – ISO 7816 and EMV 2000 (TDA8029HL/C2).
• 1 to 8 characters FIFO in reception mode
• Parity error counter in reception mode and in transmission mode with automatic retransmission
• Versatile 24-bit time-out counter for ATR and waiting times processing
• Specific ETU counter for Block Guard Time (BGT) (22 ETU in T = 1 and 16 ETU in T = 0)
• Minimum delay between two characters in reception mode:
   – In protocol T = 0:
      12 ETU (TDA8029HL/C1)
      11.8 ETU (TDA8029HL/C2).
   – In protocol T = 1:
      11 ETU (TDA8029HL/C1)
      10.8 ETU (TDA8029HL/C2).
• Supports synchronous cards which do not use C4/C8
• Current limitations on card contacts
• Supply supervisor for power-on/off reset and spikes killing
• DC/DC converter (supply voltage from 2.7 to 6 V), doubler, tripler or follower according to VCC and VDD
• Shut-down input for very low power consumption
• Enhanced ESD protection on card contacts (6 kV minimum)
• Software library for easy integration
• Communication with the host through a standard full duplex serial link at programmable baud rates
• One external interrupt input and four general purpose I/Os.

APPLICATIONS
• Portable card readers
• General purpose card readers
• EMV compliant card readers.

 

View
TDA8029 [Low power single card reader ]

other parts : TDA8029C1  TDA8029C2  TDA8029HL  TDA8029HL/C1  TDA8029HL/C2 

NXP
NXP Semiconductors.

General description
The TDA8029 is a complete one chip, low cost, low power, robust smart card reader. Its different power reduction modes and its wide supply voltage range allow its use in portable equipment. Due to specific versatile hardware, a small embedded software program allows the control of most cards available in the market. The control from the host may be done through a standard serial interface. The TDA8029 may be delivered with standard embedded software, or be masked with specific customer code. For details on software development and on available tools, please refer to application notes “AN01009” and “AN10134” for the TDA8029HL/C1. For standard embedded software, please refer to “AN10206” for the TDA8029HL/C2.

Features
■ 80C51 core with 16 kB ROM, 256 byte RAM and 512 byte XRAM
■ Specific ISO7816 UART, accessible with MOVX instructions for automatic convention processing, variable baud rate, error management at character level for T = 0 and T = 1 protocols, extra guard time, etc.
■ Specific versatile 24-bit Elementary Time Unit (ETU) counter for timing processing
during Answer To Reset (ATR) and for T = 1 protocol
■ VCC generation with controlled rise and fall times:
   ◆ 5 V ± 5 %, maximum current 65 mA
   ◆ 3 V ± 5 %, maximum current 50 mA; maximum current 65 mA if VDD > 3 V
   ◆ 1.8 V ± 5 %, maximum current 30 mA
■ Card clock generation up to 20 MHz with three times synchronous frequency doubling (fXTAL, 1⁄2fXTAL, 1⁄4fXTAL and 1⁄8fXTAL)
■ Card clock stop HIGH or LOW or 1.25 MHz from an integrated oscillator for card power reduction modes
■ Automatic activation and deactivation sequences through an independent sequencer
■ Supports asynchronous protocols T = 0 and T = 1 in accordance with:
   ◆ ISO 7816 and EMV 3.1.1 (TDA8029HL/C1 and TDA8029HL/C2)
   ◆ ISO 7816 and EMV 2000 (TDA8029HL/C2).
■ 1 to 8 characters FIFO in reception mode
■ Parity error counter in reception mode and in transmission mode with automatic retransmission
■ Versatile 24-bit time-out counter for ATR and waiting times processing
■ Specific ETU counter for Block Guard Time (BGT) (22 ETU in T = 1 and 16 ETU in T = 0)

View
8029 [TYPE N FEMALE TO TYPE N FEMALE RADIUS R/A ADAPTER ] ETC2
Unspecified

[Tensolite]

View
6318029-3 [0.6mm Free Height (FH) and GIGA Connectors ]

other parts : 1-5316076-0  1-5316077-0  1-5316135-0  1-5316135-1  1-5316318-0  1-5316318-1  1-5316559-1  1-5316560-1  1-5316562-1  1-5353134-0 

MACOM
Tyco Electronics

Tyco Electronics 0.6mm Free Height (FH) and GIGA connectors are designed for use in the parallel stacking
of printed circuit boards. These 0.6 [.024] fine pitch connectors provide the capability of varying the spacing between parallel boards, depending upon the components to be pack aged or equipment designs. They are best suited for applications where miniaturization is essential, such as notebook PCs, sub-notebook PCs, pen pads, cellular phones and communication equipment.

Product Facts
■0.6 [.024] pitch SMT connectors for parallel board stacking
■Connector sizes ranging from 50 to 280 positions
■Solder pegs included for anti-peeling
■Available packaged on “tape-and-reel” for automatic placement per EIA standards
■Surface areas provided to accommodate vacuum nozzles
■Enhanced electrical performance grounded version (GIGA) available for high speed signals
■Recognized under the Component Program of Underwriter Laboratories Inc., File No. E28476
 

View
78029013A [CMOS Manchester Encoder-Decoder ]

other parts : 7802901JA  HD-15530  HD-15530-8  HD-15530-9  HD1-15530-8  HD1-15530-9  HD3-15530-9  HD4-15530-8  HD4-15530-9 

Intersil
Intersil

Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions.

Features
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V

View
7802901JA [CMOS Manchester Encoder-Decoder ]

other parts : 78029013A  HD-15530  HD-15530-8  HD-15530-9  HD1-15530-8  HD1-15530-9  HD3-15530-9  HD4-15530-8  HD4-15530-9 

Intersil
Intersil

Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions.

Features
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V

View
S80296 [COMMERCIAL CHMOS 16-BIT MICROCONTROLLER ]

other parts : 80296SA  80C296SA  S80296SA  S80296SA-50  S80296SA50 

Intel
Intel

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. The device has hardware and instructions to support various digital signal processing algorithms.

■50 MHz Operation†
■6 Mbytes of Linear Address Space
■512 Bytes of Register RAM
■2 Kbytes of Code/Data RAM
■Register-register Architecture
■Footprint and Functionally Compatible Upgrade for the 8XC196NP and 80C196NU
■Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier
■32 I/O Port Pins
■19 Interrupt Sources, 14 with Programmable Priorities
■4 External Interrupt Pins and NMI Pin
■2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability
■3 Pulse-width Modulator (PWM) Outputs with High Drive Capability
■Full-duplex Serial Port with Dedicated Baud-rate Generator
■Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select
— Programmable Wait States (0–15) for Each Chip Select
— Programmable Bus Width (8- or 16-bit) for Each Chip Select
— Programmable Address Range for Each Chip Select
■Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels
■Multiply and Accumulate Executes in 80 ns Using the 40-bit Hardware Accumulator
■880 ns 32/16 Unsigned Division
■100-pin QFP Package
■Complete System Development Support
■High-speed CHMOS Technology

View
80296SA [COMMERCIAL CHMOS 16-BIT MICROCONTROLLER ]

other parts : 80C296SA  S80296  S80296SA  S80296SA-50  S80296SA50 

Intel
Intel

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. The device has hardware and instructions to support various digital signal processing algorithms.

■50 MHz Operation†
■6 Mbytes of Linear Address Space
■512 Bytes of Register RAM
■2 Kbytes of Code/Data RAM
■Register-register Architecture
■Footprint and Functionally Compatible Upgrade for the 8XC196NP and 80C196NU
■Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier
■32 I/O Port Pins
■19 Interrupt Sources, 14 with Programmable Priorities
■4 External Interrupt Pins and NMI Pin
■2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability
■3 Pulse-width Modulator (PWM) Outputs with High Drive Capability
■Full-duplex Serial Port with Dedicated Baud-rate Generator
■Chip-select Unit
— 6 Chip-select Pins
— Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select
— Programmable Wait States (0–15) for Each Chip Select
— Programmable Bus Width (8- or 16-bit) for Each Chip Select
— Programmable Address Range for Each Chip Select
■Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels
■Multiply and Accumulate Executes in 80 ns Using the 40-bit Hardware Accumulator
■880 ns 32/16 Unsigned Division
■100-pin QFP Package
■Complete System Development Support
■High-speed CHMOS Technology

View
1 2 3 4 5
Share Link : 

HOME




Language : 한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home ][ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]