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LPC1752FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751  LPC1752  LPC1754  LPC1756  LPC1758  LPC1759  LPC1759FBD80  LPC1758FBD80  LPC1756FBD80  LPC1754FBD80 

Philips
Philips Electronics

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 2 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 52 general purpose I/O pins.

Features
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
   ♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
   ♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
      These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
   AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
   ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
   ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
   ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
   ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
   ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
   ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
   ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
   ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
   ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
   ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
   ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
   ♦ Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
   ♦ One motor control PWM with support for three-phase motor control.
   ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
   ♦ One standard PWM/timer block with external count input.
   ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
   ♦ Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
   ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
   ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
   ♦ Each peripheral has its own clock divider for further power savings.
■ Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.
■ Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
■ Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
■ Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
■ Single 3.3 V power supply (2.4 V to 3.6 V).
■ One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.
■ Non-maskable Interrupt (NMI) input.
■ The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes.
■ Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).
■ Brownout detect with separate threshold for interrupt and forced reset.
■ Power-On Reset (POR).
■ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
■ 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.
■ PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
■ USB PLL for added flexibility.
■ Code Read Protection (CRP) with different security levels.
■ Unique device serial number for identification purposes.
■ Available as 80-pin LQFP package (12 mm × 12 mm × 1.4 mm).

Applications
■ eMetering
■ Lighting
■ Industrial networking
■ Alarm systems
■ White goods
■ Motor control

 

View
LPC1751FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751  LPC1752  LPC1754  LPC1756  LPC1758  LPC1759  LPC1759FBD80  LPC1758FBD80  LPC1756FBD80  LPC1754FBD80 

Philips
Philips Electronics

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 2 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 52 general purpose I/O pins.

Features
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
   ♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
   ♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
      These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
   AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
   ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
   ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
   ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
   ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
   ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
   ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
   ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
   ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
   ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
   ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
   ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
   ♦ Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
   ♦ One motor control PWM with support for three-phase motor control.
   ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
   ♦ One standard PWM/timer block with external count input.
   ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
   ♦ Watchdog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
   ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
   ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
   ♦ Each peripheral has its own clock divider for further power savings.
■ Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.
■ Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
■ Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
■ Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
■ Single 3.3 V power supply (2.4 V to 3.6 V).
■ One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.
■ Non-maskable Interrupt (NMI) input.
■ The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes.
■ Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).
■ Brownout detect with separate threshold for interrupt and forced reset.
■ Power-On Reset (POR).
■ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
■ 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.
■ PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
■ USB PLL for added flexibility.
■ Code Read Protection (CRP) with different security levels.
■ Unique device serial number for identification purposes.
■ Available as 80-pin LQFP package (12 mm × 12 mm × 1.4 mm).

Applications
■ eMetering
■ Lighting
■ Industrial networking
■ Alarm systems
■ White goods
■ Motor control

 

View
LPC1751FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80,551  LPC1752FBD80  LPC1752FBD80,551  LPC1754FBD80  LPC1754FBD80,551  LPC1756FBD80  LPC1756FBD80/CP327  LPC1758FBD80  LPC1758FBD80Y  LPC1759FBD80 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
LPC1752FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80  LPC1751FBD80,551  LPC1752FBD80,551  LPC1754FBD80  LPC1754FBD80,551  LPC1756FBD80  LPC1756FBD80/CP327  LPC1758FBD80  LPC1758FBD80Y  LPC1759FBD80 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
LPC1754FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80  LPC1751FBD80,551  LPC1752FBD80  LPC1752FBD80,551  LPC1754FBD80,551  LPC1756FBD80  LPC1756FBD80/CP327  LPC1758FBD80  LPC1758FBD80Y  LPC1759FBD80 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
LPC1756FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80  LPC1751FBD80,551  LPC1752FBD80  LPC1752FBD80,551  LPC1754FBD80  LPC1754FBD80,551  LPC1756FBD80/CP327  LPC1758FBD80  LPC1758FBD80Y  LPC1759FBD80 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
LPC1758FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80  LPC1751FBD80,551  LPC1752FBD80  LPC1752FBD80,551  LPC1754FBD80  LPC1754FBD80,551  LPC1756FBD80  LPC1756FBD80/CP327  LPC1758FBD80Y  LPC1759FBD80 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
LPC1759FBD80 [32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN ]

other parts : LPC1751FBD80  LPC1751FBD80,551  LPC1752FBD80  LPC1752FBD80,551  LPC1754FBD80  LPC1754FBD80,551  LPC1756FBD80  LPC1756FBD80/CP327  LPC1758FBD80  LPC1758FBD80Y 

NXP
NXP Semiconductors.

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

Features and benefits
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
   (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit
   (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
♦ Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
■ These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
 
■ Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between the CPU and DMA.
■ Serial interfaces:
 ♦ On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA controller.
 ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
 ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
 ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
 ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
 ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
 ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
 ♦ On the LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ Other peripherals:
 ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.
 ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.
 ♦ On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
 Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
 ♦ One motor control PWM with support for three-phase motor control.
 ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
 ♦ One standard PWM/timer block with external count input.
 ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
 ♦ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.
 ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
 ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
    ♦ Each peripheral has its own clock divider for further power savings.

 

View
GE28F160C3BD80 [Intel Advanced+ Boot Block Flash Memory (C3) ]

other parts : 28F160C3  28F320C3  28F640C3  28F800C3  GE28F160C3BA100  GE28F160C3BA110  GE28F160C3BA70  GE28F160C3BA80  GE28F160C3BA90  GE28F160C3BC100 

Intel
Intel

Device Description
This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features, packaging, signal naming, and device architecture.

Product Overview
The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks.

Product Features
■ Flexible SmartVoltage Technology
   —2.7 V– 3.6 V Read/Program/Erase
   —12 V for Fast Production Programming
■ 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
   —Reduces Overall System Power
■ High Performance
   —2.7 V– 3.6 V: 70 ns Max Access Time
■ Optimized Architecture for Code Plus Data Storage
   —Eight 4 Kword Blocks, Top or Bottom Parameter Boot
   —Up to One Hundred-Twenty-Seven 32 Kword Blocks
   —Fast Program Suspend Capability
   —Fast Erase Suspend Capability
■ Flexible Block Locking
   —Lock/Unlock Any Block
   —Full Protection on Power-Up
   —WP# Pin for Hardware Block Protection
■ Low Power Consumption
   —9 mA Typical Read
   —7 A Typical Standby with Automatic Power Savings Feature (APS)
■ Extended Temperature Operation
   —–40 °C to +85 °C
■ 128-bit Protection Register
   —64 bit Unique Device Identifier
   —64 bit User Programmable OTP Cells
■ Extended Cycling Capability
   —Minimum 100,000 Block Erase Cycles
■ Software
   —Intel® Flash Data Integrator (FDI)
   —Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice)
   —Intel Basic Command Set
   —Common Flash Interface (CFI)
■ Standard Surface Mount Packaging
   —48-Ball µBGA*/VFBGA
   —64-Ball Easy BGA Packages
   —48-Lead TSOP Package
■ ETOX™ VIII (0.13 µm) Flash Technology
   —16, 32 Mbit
■ ETOX™ VII (0.18 µm) Flash Technology
   —16, 32, 64 Mbit
■ ETOX™ VI (0.25 µm) Flash Technology
   —8, 16 and 32 Mbit

 

View
GE28F320C3BD80 [Intel Advanced+ Boot Block Flash Memory (C3) ]

other parts : 28F160C3  28F320C3  28F640C3  28F800C3  GE28F160C3BA100  GE28F160C3BA110  GE28F160C3BA70  GE28F160C3BA80  GE28F160C3BA90  GE28F160C3BC100 

Intel
Intel

Device Description
This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features, packaging, signal naming, and device architecture.

Product Overview
The C3 device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’s memory map. The rest of the memory array is grouped into 32 Kword main blocks.

Product Features
■ Flexible SmartVoltage Technology
   —2.7 V– 3.6 V Read/Program/Erase
   —12 V for Fast Production Programming
■ 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
   —Reduces Overall System Power
■ High Performance
   —2.7 V– 3.6 V: 70 ns Max Access Time
■ Optimized Architecture for Code Plus Data Storage
   —Eight 4 Kword Blocks, Top or Bottom Parameter Boot
   —Up to One Hundred-Twenty-Seven 32 Kword Blocks
   —Fast Program Suspend Capability
   —Fast Erase Suspend Capability
■ Flexible Block Locking
   —Lock/Unlock Any Block
   —Full Protection on Power-Up
   —WP# Pin for Hardware Block Protection
■ Low Power Consumption
   —9 mA Typical Read
   —7 A Typical Standby with Automatic Power Savings Feature (APS)
■ Extended Temperature Operation
   —–40 °C to +85 °C
■ 128-bit Protection Register
   —64 bit Unique Device Identifier
   —64 bit User Programmable OTP Cells
■ Extended Cycling Capability
   —Minimum 100,000 Block Erase Cycles
■ Software
   —Intel® Flash Data Integrator (FDI)
   —Supports Top or Bottom Boot Storage, Streaming Data (e.g., voice)
   —Intel Basic Command Set
   —Common Flash Interface (CFI)
■ Standard Surface Mount Packaging
   —48-Ball µBGA*/VFBGA
   —64-Ball Easy BGA Packages
   —48-Lead TSOP Package
■ ETOX™ VIII (0.13 µm) Flash Technology
   —16, 32 Mbit
■ ETOX™ VII (0.18 µm) Flash Technology
   —16, 32, 64 Mbit
■ ETOX™ VI (0.25 µm) Flash Technology
   —8, 16 and 32 Mbit

 

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