3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator
The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8âlead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.
The VBB output allows this EPT21 to be cap coupled in either singleâended or differential input mode. When singleâended cap coupled, VBB output is tied to the D input and D is driven for a nonâinverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 μF capacitor. For additional information see AND8020/D. For a singleâended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a singleâended direct connection or port to another device.
Features
⢠1.4 ns Typical Propagation Delay
⢠Maximum Frequency > 275 MHz Typical
⢠LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
⢠24 mA TTL outputs
⢠Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
⢠The 100 Series Contains Temperature Compensation
⢠VBB Output
⢠PbâFree Packages are Available
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