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Part Name  

108296138 Datasheet

Part Name Description Manufacturer
108296138 AmbassadorTM T8100A, T8102, and T8105 H.100/H.110 Interface and Time-Slot Interchangers Agere
Agere -> LSI Corporation Agere
Other PDF  not available.
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T8100A-SC-DB image

Introduction
This advisory describes a flaw in some devices that the initial factory test program did not detect. The flaw exists in some version 2 and version 3 T8100A, T8102, and T8105 devices in both the SQFP and BGA package types. An enhanced factory test program has been in place since January 2000, and all devices shipped after this date are good devices.

Description
These products in the Ambassador T8100 family provide a complete time-slot switch and an interface for the H.100/H.110 time-division multiplexed (TDM) buses. The T8100 family includes devices with hier archical switching as well as a capacity of up to 512 local to H.100 connections. The hierarchical switch ing allows up to 1024 local connections without using H.100 bus bandwidth. The family also includes the T8102 device for a low-cost solution in nonhierarchical systems.

Features
■ Complete solution for interfacing board-level cir cuitry to the H.100 telephony bus
■ H.100 compliant interface; all mandatory signals
■ Programmable connections to any of the 4096 time slots on the H.100 bus
■ Up to 16 local serial inputs and 16 local serial outputs, programmable for 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s operation per CHI specifications
■ Programmable switching between local time slots, up to 1024 connections
■ Subrate switching of nibbles, dibits, or bits
■ Backward compatible to T8100 through software
■ Programmable switching between local time slots and H.100 bus, up to 512 (T8102, T8105 only) connections
■ Choice of frame integrity or minimum latency switching on a per-time-slot basis
   — Frame integrity to ensure proper switching of wideband data
   — Minimum latency switching to reduce delay in voice channels
■ On-chip phase-locked loop (PLL) for H.100, MVIP*, or SC-Bus clock operation in master or slave clock modes
■ Serial TDM bus rate and format conversion between most standard buses
■ Optional 8-bit parallel input and/or 8-bit parallel output for local TDM interfaces
■ High-performance microprocessor interface
   — Provides access to device configuration regis ters and to time-slot data
   — Supports both Motorola† nonmultiplexed and Intel‡ multiplexed/nonmultiplexed modes
■ Two independently programmable groups of up to 12 framing signals each
■ Devices available in 0.25 micron technology
■ 3.3 V supply with 5 V tolerant inputs and TTL-com patible outputs
■ Boundary-scan testing support
■ 208-pin, plastic SQFP package
■ 217-ball BGA package (industrial temperature range)

 

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