The 74AC11239 circuit is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The 74AC11239 is comprised of two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74AC11239 is characterized for operation from – 40°C to 85°C.
• Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
• Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
• Flow-Through Architecture to Optimize PCB Layout
• Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-μm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs