General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flopâs Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
â ICC reduced by 50%
â Ideal for addressable register applications
â Clock enable for address and data synchronization applications
â Eight edge-triggered D-type flip-flops
â Buffered common clock
â Outputs source/sink 24 mA
â See 273 for master reset version
â See 373 for transparent latch version
â See 374 for 3-STATE version
â ACT377 has TTL-compatible inputs
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