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74ACT109 데이터시트

부품명74ACT109 ON-Semiconductor
ON Semiconductor ON-Semiconductor
상세내역Dual JK Positive Edge−Triggered Flip−Flop
Other Doc.  2001  
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The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

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74ACT109 관련 기타 제조 업체 검색

SN54LS109AJ DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP View Motorola => Freescale
SN54LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP View Motorola => Freescale
74F109 Dual JK Positive Edge-Triggered Flip-Flop View Fairchild Semiconductor
74AC109 Dual JK positive edge-triggered flip-flop View Motorola => Freescale
74AC109 Dual JK Positive Edge−Triggered Flip−Flop View ON Semiconductor
MC74F112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View Motorola => Freescale
74AC109 Dual JK Positive Edge-Triggered Flip-Flop View Fairchild Semiconductor
SN54LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View Motorola => Freescale
74F113 Dual JK Negative Edge-Triggered Flip-Flop View Fairchild Semiconductor
MC74AC113 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View Motorola => Freescale

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