General Description
These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.
Features
â Independent registers for A and B buses
â Multiplexed real-time and stored data
â Choice of non-inverting and inverting data paths
74F651 inverting
74F652 non-inverting
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