General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and benefits
â Complies with JEDEC standard no. 7A
â Input levels:
â The 74HC107: CMOS levels
â The 74HCT107: TTL levels
â ESD protection:
â HBM JESD22-A114F exceeds 2000 V
â MM JESD22-A115-A exceeds 200 V
â Multiple package options
â Specified from -40°C to +85°C and from -40°C to +125°C
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