DatasheetQ Logo
Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

ADS6422 Datasheet - STMicroelectronics

ADS6422 Datasheet PDF STMicroelectronics

Part Name
ADS6422

Other PDF
  not available.

page
75 Pages

File Size
2.6 MB

MFG CO.
ST-Microelectronics
STMicroelectronics ST-Microelectronics

DESCRIPTION
The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

FEATURES
• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5dB Coarse Gain and up to 6dB
   Programmable Fine Gain for SFDR/SNR
   Trade-Off
• Serialized LVDS Outputs with Programmable
   Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS
   Clock Inputs and Amplitude down to 400 mVPP
• Internal Reference with External Reference
   Support
• No External Decoupling Required for
   References
• 3.3-V Analog and Digital Supply
• 64 QFN Package (9 mm × 9 mm)
• Pin Compatible 12-Bit Family (ADS642X -
   SLAS532)
• Feature Compatible Dual Channel Family
   (ADS624X - SLAS542, ADS644X - SLAS543)

APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

Part Name
Description
PDF
MFG CO.
Quad, 12-Bit, 80 MSPS/105 MSPS/125 MSPS, Serial LVDS 1.8 V ADC ( Rev : Rev0 )
Analog Devices
Quad, 12-Bit, 80 MSPS/105 MSPS/125 MSPS, Serial LVDS 1.8 V ADC
Analog Devices
Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter
Analog Devices
14-Bit, 105/125 MSPS, IF Sampling ADC
Analog Devices
Quad, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS 1.8 V ADC ( Rev : RevF )
Analog Devices
12-Bit, 80 MSPS/105 MSPS ADC
Analog Devices
14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) ( Rev : V2 )
Analog Devices
14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Analog Devices
Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC
Analog Devices
Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC ( Rev : RevE )
Analog Devices

Share Link: 

All Rights Reserved© datasheetq.com  [Privacy Policy ] [ Request Datasheet] [Contact Us]