QUAD EIA-422/423 Line Receiver with Three-State Outputs
Motorolaâ²s Quad EIAâ422/3 Receiver features four independent receiver chains which comply with EIA Standards for the Electrical Characteristics of Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs are 74LS compatible, threeâstate structures which are forced to a high impedance state when Pin 4 is a Logic â0â and Pin 12 is a Logic â1.â A PNP device buffers each output control pin to assure minimum loading for either Logic â1â or Logic â0â inputs. In addition, each receiver chain has internal hysteresis circuitry to improve noise margin and discourage output instability for slowly changing input waveforms. A summary of AM26LS32 features include:
⢠Four Independent Receiver Chains
⢠ThreeâState Outputs
⢠High Impedance Output Control Inputs (PIA Compatible)
⢠Internal Hysteresis â 30 mV (Typical) @ Zero Volts Common Mode
⢠Fast Propagation Times â 25 ns (Typical)
⢠TTL Compatible
⢠Single 5.0 V Supply Voltage
⢠FailâSafe InputâOutput Relationship. Output Always High When Inputs Are Open, Terminated or Shorted
⢠6.0 k Minimum Input Impedance
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