The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK#.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of a BankActivate command, which is then followed by a Read or Write command.
The EM6A9320 provides programmable Read or Write burst lengths of 2, 4, 8 and full page. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
• Fast clock rate: 250/200/166 MHz
• Differential Clock CK & CK# input
• 4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
• DLL aligns DQ and DQS transitions
• Edge aligned data & DQS output
• Center aligned data & DQS input
• 4 internal banks, 1M x 32-bit for each bank
• Programmable mode and extended mode registers
- CAS Latency: 2, 2.5, 3, 4
- Burst length: 2, 4, 8, and Full Page
- Burst Type: Sequential & Interleave
• Full page burst length for sequential type only
• Start address of full page burst should be even
• All inputs except DQ’s & DM are at the positive
edge of the system clock
• No Write-Interrupted by Read function
• 4 individual DM control for write masking only
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 32ms
• Power supplies :
VDD = 2.5V ± 5%
VDDQ = 2.5V ± 5%
• Interface : SSTL_2 I/O compatible
• Standard 144-ball FBGA package
• Pb-free package is availiable