Functional Description
Applications
The GS832218/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Features
⢠FT pin for user-configurable flow through or pipeline operation
⢠Single/Dual Cycle Deselect selectable
⢠IEEE 1149.1 JTAG-compatible Boundary Scan
⢠ZQ mode pin for user-selectable high/low output drive
⢠2.5 V +10%/â10% core power supply
⢠3.3 V +10%/â10% core power supply
⢠2.5 V or 3.3 V I/O supply
⢠LBO pin for Linear or Interleaved Burst mode
⢠Internal input resistors on mode pins allow floating mode pins
⢠Default to SCD x18/x36 Interleaved Pipeline mode
⢠Byte Write (BW) and/or Global Write (GW) operation
⢠Internal self-timed write cycle
⢠Automatic power-down for portable applications
⢠JEDEC-standard 119-, 165-, and 209-bump BGA package
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