Features
⢠Single Cycle Deselect (SCD) operation
⢠2.5 V or 3.3 V +10%/â10% core power supply
⢠2.5 V or 3.3 V I/O supply
⢠LBO pin for Linear or Interleaved Burst mode
⢠Internal input resistors on mode pins allow floating mode pins
⢠Default to Interleaved Pipeline mode
⢠Byte Write (BW) and/or Global Write (GW) operation
⢠Internal self-timed write cycle
⢠Automatic power-down for portable applications
⢠JEDEC-standard 100-lead TQFP package
Applications
 The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
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