Functional Description
Applications
The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
1.11 9/2000Features
⢠FT pin for user-configurable flow through or pipelined operation
⢠Single Cycle Deselect (SCD) Operation
⢠IEEE 1149.1 JTAG-compatible Boundary Scan
⢠On-chip write parity checking; even or odd selectable
⢠3.3 V +10%/â5% core power supply
⢠2.5 V or 3.3 V I/O supply
⢠LBO pin for Linear or Interleaved Burst mode
⢠Internal input resistors on mode pins allow floating mode pins
⢠Default to Interleaved Pipeline mode
⢠Byte Write (BW) and/or Global Write (GW) operation
⢠Common data inputs and data outputs
⢠Clock Control, registered, address, data, and control
⢠Internal self-timed write cycle
⢠Automatic power-down for portable applications
⢠100-lead TQFP package
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