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MBM29F200BC-55PF Datasheet - Fujitsu

MBM29F200BC-55PF Datasheet PDF Fujitsu

Part Name
MBM29F200BC-55PF

Other PDF
  not available.

page
48 Pages

File Size
328.4 kB

MFG CO.
Fujitsu
Fujitsu Fujitsu

■ GENERAL DESCRIPTION
The MBM29F200TC/BC is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. The MBM29F200TC/BC is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard MBM29F200TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.

■ FEATURES
• Single 5.0 V read, write, and erase
    Minimizes system level power requirements
• Compatible with JEDEC-standard commands
    Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
    48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
    44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
    55 ns maximum access time
• Sector erase architecture
    One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.
    Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
    T = Top sector
    B = Bottom sector
• Embedded EraseTM Algorithms
    Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
    Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
    Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit ≤ 3.2 V
• Erase Suspend/Resume
    Suspends the erase operation to allow a read in another sector within the same device
• Hardware RESET pin
    Resets internal state machine to the read mode
• Sector protection
    Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
    Hardware method temporarily enables any combination of sectors from write on erase operations.

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