The MC14015B dual 4âbit static shift register is constructed with MOS Pâchannel and Nâchannel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4âstate serialâinput/parallelâoutput registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D masterâslave flipâflops. Data is shifted from one stage to the next during the positiveâgoing clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serialâtoâparallel conversion where low power dissipation and/or noise immunity is desired.
⢠Diode Protection on All Inputs
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Logic EdgeâClocked FlipâFlop Design â
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going edge of the clock pulse.
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower Schottky
TTL Load Over the Rated Temperature Range.
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