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MT49H16M16 Datasheet

Part NameMT49H16M16(2002) Micron
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MT49H16M16(2002) Datasheet PDF : MT49H16M16 pdf     

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The Micron® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.

• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Cyclic bank addressing for maximum data out bandwidth
• Non-multiplexed addresses
• Non-interruptible sequential burst of two (2-bit
   prefetch) and four (4-bit prefetch) DDR
• Target 600 Mb/s/p data rate
• Programmable Read Latency (RL) of 5-8
• Data valid signal (DVLD) activated as read data is available
• Data Mask signals (DM0/DM1) to mask first and
   second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• Pseudo-HSTL 1.8V I/O Supply
• Internal Auto Precharge
• Refresh requirements: 32ms at 100°C junction
   temperature (8K refresh for each bank, 64K refresh
   command must be issued in total each 32ms)

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