FEATURES
⢠Dual-Issue symmetric superscalar microprocessor
⢠500MHz max CPU frequency
⢠Capable of issuing two instructions per clock cycle
⢠Integrated primary and secondary caches
⢠16KB Instruction, 16KB Data, and 256KB on-chip secondary
⢠All are 4-way set associative with 32-byte line size
⢠Per-line locking in primary and secondary caches
⢠Fast Packet Cache⢠increases system efficiency in networking applications
⢠Integrated external cache controller
⢠Allows up to 8Mbyte of external cache for applications with large data sets
⢠High-performance system interface
⢠1000 Mbyte per-second peak throughput
⢠125 MHz max. freq., multiplexed address/data bus (SysAD)
⢠Supports two outstanding reads with out-of-order return
⢠High-performance floating-point unit
⢠1000 MFLOPS maximum
⢠IEEE754 compliant single and double precision floating-point operations
⢠64-bit MIPS instruction set architecture
⢠Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
⢠Single-cycle floating-point multiply add
⢠Integrated memory management unit
⢠Fully associative TLB
⢠64/48 dual entries map 128/96 pages
⢠Variable page size
⢠Embedded application enhancements
⢠Fourteen fully prioritized vectored interrupts-10 external, 2 internal, 2 software
⢠Specialized DSP integer Multiply Accumulate instructions (MAD/MADU), and three-operand Multiply instruction (MUL)
⢠I and D Test/Break-point (Watch) registers for emulation and debug
⢠Performance counter for system and software tuning and debug
APPLICATIONS
⢠Voice Gateways
⢠Multi-Service Access Platforms
⢠DSLAMs/Access Concentrators
⢠Remote Access Switches
⢠Web Switches
⢠Layer 3 Switches
⢠Backbone Switches/Routers
⢠RAIDs
⢠Set Top Boxes
⢠Networked Printers
⢠Cellular Base Stations
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