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SMJ32C6411 Datasheet

Part NameSMJ32C6411 TI
Texas Instruments TI
DescriptionFIXED-POINT DIGITAL SIGNAL PROCESSORS
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The TMS320C64x™ DSPs (including the SMJ320C6414, SMJ320C6415, and SMJ320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™†) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunctional applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

● Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
   − 2-, 1.67-, 1.39-ns Instruction Cycle Time
   − 600-MHz Clock Rate
   − Eight 32-Bit Instructions/Cycle
   − Twenty-Eight Operations/Cycle
   − 4800 MIPS
   − Fully Software-Compatible With C62x
   − C6414/15/16 Devices Pin-Compatible
● VelociTI.2 Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
   − Eight Highly Independent Functional
      Units With VelociTI.2™ Extensions:
      − Six ALUs (32-/40-Bit), Each Supports
         Single 32-Bit, Dual 16-Bit, or Quad
         8-Bit Arithmetic per Clock Cycle
      − Two Multipliers Support
         Four 16 x 16-Bit Multiplies
         (32-Bit Results) per Clock Cycle or
         Eight 8 x 8-Bit Multiplies
         (16-Bit Results) per Clock Cycle
   − Non-Aligned Load-Store Architecture
   − 64 32-Bit General-Purpose Registers
   − Instruction Packing Reduces Code Size
   − All Instructions Conditional
● Instruction Set Features
   − Byte-Addressable (8-/16-/32-/64-Bit Data)
   − 8-Bit Overflow Protection
   − Bit-Field Extract, Set, Clear
   − Normalization, Saturation, Bit-Counting
● Viterbi Decoder Coprocessor (VCP) [C6416]
   − Supports Over 500 7.95-Kbps AMR
   − Programmable Code Parameters
● Turbo Decoder Coprocessor (TCP) [C6416]
   − Supports up to Six 2-Mbps 3GPP (6 Iterations)
   − Programmable Turbo Code and Decoding Parameters
● L1/L2 Memory Architecture
   − 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
   − 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
   − 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation) (Continue....)

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