â High Performance 16-bit CPU
â CPU Frequency: 0 to 50 MHz
â 40ns instruction cycle time at 50-MHz CPU clock
â 4-stage pipeline
â Register-based design with multiple variable register banks
â Enhanced boolean bit manipulation facilities
â Additional instructions to support HLL and operating systems
â Single-cycle context switching support
â 1024 bytes on-Chip special function register area
â Memory Organisation
â 1KByte on-chip RAM
â Up to 16 MBytes linear address space for code and data (1 MByte with SSP used)
â External Memory Interface
â Programmable external bus characteristics for different address ranges
â 8-bit or 16-bit external data bus
â Multiplexed or demultiplexed external address/data buses
â Five programmable chip-select signals
â Hold and hold-acknowledge bus arbitration support
â One Channel PWM Unit
â Fail Safe Protection
â Programmable watchdog timer
â Oscillator Watchdog
â Interrupt
â 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC)
â 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns
â Timers
â Two multi-functional general purpose timer units with 5 timers
â Clock Generation via on-chip PLL, or via direct or prescaled clock input
â Serial Channels
â Synchronous/asynchronous
â High-speed-synchronous serial port SSP
â Up to 77 general purpose I/O lines
â No bootstrap loader
â Electrical Characteristics
â 5V Tolerant I/Os
â 5V Fail-Safe Inputs (Port 5)
â Power: 3.3 Volt +/-0.3V
â Idle and power down modes
â Support
â C-compilers, macro-assembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyser disassemblers, programming boards
â Package
â 100-Pin Thin Quad Flat Pack (TQFP)
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