GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output.
FEATURES
⢠Complete 1.3 GHz single chip system
⢠Four PNP band switch buffers (40 mA)
⢠33 V output tuning voltage
⢠In-lock detector
⢠5-step ADC
⢠15-bit programmable divider
⢠Programmable reference divider ratio (512, 640 or 1024)
⢠Programmable charge-pump current (60 or 280 µA)
⢠Programmable automatic charge-pump current switch
⢠Varicap drive disable
⢠Universal bus protocol I2C-bus or 3-wire bus:
â bus protocol for 18 or 19 bits transmission (3-wire bus)
â extra protocol for 27 bits for test and features (3-wire bus)
â address plus 4 data bytes transmission (I2C-bus write mode)
â address plus 1 status byte transmission (I2C-bus read mode)
â three independent I2C-bus addresses
⢠Low power and low radiation.
APPLICATIONS
⢠TV tuners and front ends
⢠VCR tuners.
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