Description
The V62C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three state outputs are TTL compatible and allow for
direct interfacing with common system bus structures.
Features
â High-speed: 35, 70 ns
â Ultra low DC operating current of 5mA (max.)
â Low Power Dissipation:
– TTL Standby: 3 mA (Max.)
– CMOS Standby: 20 µA (Max.)
â Fully static operation
â All inputs and outputs directly compatible
â Three state outputs
â Ultra low data retention current (VCC= 2V)
â Single 5V ±10% Power Supply
â Packages
– 28-pin TSOP (Standard)
– 28-pin 600 mil PDIP
– 28-pin 330 mil SOP (450 mil pin-to-pin)
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