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5962D9317710VNC Datasheet - Atmel

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Description
MFG CO.
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Description
The M672061H implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information are required for the Atmel FIFOs. Address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The Retransmit pin resets the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system.

Features
• First-in First-out Dual Port Memory
• 16384 bits x 9 Organization
• Fast Flag and Access Times: 15, 30 ns
• Wide Temperature Range: -55°C to +125°C
• Programmable Half Full Flag
• Fully Expandable by Word Width or Depth
• Asynchronous Read/Write Operations
• Empty, Full and Half Flags in Single Device Mode
• Retransmit Capability
• Bi-directional Applications
• Battery Back-up Operation: 2V Data Retention
• TTL Compatible
• Single 5V + 10% Power Supply
• No Single Event Latch Up Below an LET threshold of 80 MeV/mg/cm2
• Tested up to a Total Dose of 30 Krads (according to MIL-STD-883 TM1019)
• Quality grades: QML Q and V with SMD 5962-93177 and ESSC with Specification 9301/48

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Part Name
Description
PDF
MFG CO.
Rad. Tolerant High Speed 16 Kb x 9 Parallel FIFO
Atmel Corporation
Rad. Tolerant High Speed 4 Kb x 9 Parallel FIFO
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Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM
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Rad. Tolerant High Speed 8 Kb x 16 Dual Port RAM ( Rev : 2007 )
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8K x 9 FIFO, 16K x 9 FIFO 32K x 9 FIFO with Programmable Flags
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CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9
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CMOS PARALLEL-SERIAL FIFO 2,048 x 9 and 4,096 x 9
Integrated Device Technology

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