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5962F9863201VXC Datasheet - Intersil

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MFG CO.
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Radiation Hardened Dual J-K Flip-Flop with Set and Reset

The Radiation Hardened ACS109MS is a Dual J-K Flip Flop with Set and Reset. These Flip-Flops have independent J, K, Set, Reset, and Clock inputs and Q and Q outputs. The outputs change state on the positive-going transition of the clock. Set and Reset are accomplished asynchronously by Low-level inputs. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times.

Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL= (0.3)(VCC), VIH= (0.7)(VCC)
• Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns (Max)

Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs

Page Link's: 1  2 
 

Part Name
Description
PDF
MFG CO.
Dual “J-K” Flip-Flop with Set and Reset
Intersil
Dual J-K Flip-Flop with Set and Reset
ON Semiconductor
Dual J-K Flip-Flop with Set and Reset
IK Semicon Co., Ltd
Dual J-K Flip-Flop with Set and Reset
Motorola => Freescale
Dual “J-K” Flip-Flop with Set and Reset
Intersil
Dual J-K Flip-Flop with Set and Reset
System Logic Semiconductor
Radiation Hardened Dual J-K Flip-Flop
Intersil
Radiation Hardened Dual J-K Flip-Flop
Intersil
Dual J-K Flip-Flop with Set and Reset
Integral Corp.
Dual J-K Flip-Flop with Set and Reset
IK Semicon Co., Ltd

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