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Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Lead-free package options

Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Lead-free package options

Description : Voltage Controlled Crystal Oscillator

Description
Vectron’s V-Type Voltage Controlled Crystal Oscillator (VCXO) is a quartz stabilized square wave generator with a CMOS output and is tested at CMOS and TTL (5.0 volt operation) logic levels.
The V-Type’s small footprint and low profile make it ideally suitable for PCMCIA applications as well as any other where size is limited but performance is required.

Features
• Output frequencies to 80.000 MHz
• 5.0 or 3.3 V operation
• Tri-State Output
• Low jitter < 6ps rms
• VCXO with CMOS outputs
• APR to 100 ppm
• 0/70 or –40/85 °C temperature range
• Hermetically sealed ceramic SMD package

Applications
• SONET/SDH
• DWDM
• xDSL/PCMCIA cards
• Digital Video

Description : METALLIZED POLYESTER

EFC Series 1313 are metallized polyester capacitors. This series offers the advantage of small size, self healing and low cost. Suggested applications include: medical electronics, telecommunications and high voltage power supplies. Packaging options include: wrap and fill (TF, TC), radial lead box (EFR), axial lead (EC, EF). Application options include: high voltage (HV), "AC" across the line (AC), noise suppression (RC) and switching power supply (SP).
   
1. TEMPERATURE RANGE
    - 55 °C to + 85 °C at rated voltage.
    To 125 °C at 50% derating.
2. CAPACITANCE
    Capacitors < 1.0 MFD shall be measured
    at 1 KHz + 20 HZ. Capacitors >1.0 MFD
    shall be measured at 120 HZ. Measurements
    shall be taken at 25 °C.
3. DIELECTRIC STRENGTH
    At 25 °C, 150% of rated voltage when applied
    terminal to terminal for one minute through a
    current limiting resistance.
4. INSULATION RESISTANCE
    At 25 °C after 2 minutes charge time at rated voltage
    or 500 VDC, whichever is less, the minimum IR shall
    be 30,000 Megohm-Microfarad, but need not exceed
    50,000 Megohms for voltages greater than 50 VDC,
    and 15,000 Megohm-Microfarads, but need not exceed
    30,000 Megohms for 50 VDC or less.
5. HUMIDITY RESISTANCE
    Series 1313 shall meet the requirements
    of MIL-STD. 202C, Method 103B.
6. DISSIPATION FACTOR
    Shall be 1.0 % max. when measured as in Par. 2.
7. LIFE TEST
    Will withstand the application of 150% rated voltage at +125 °C for 250 hours
    with not more than one failure in 12 permitted.
   

Description : DDR2 Registered Memory Modules

Description
The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte), 128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into 240 pin connector sockets.

Low Profile 240-pin Registered DDR2 SDRAM Modules
512 MByte, 1 GByte & 2 GByte Modules PC2-3200R, PC2-4300R

• 240-pin Registered 8-Byte ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications
• One rank 64Mb x 72, 128Mb x 72 and two ranks 128Mb × 72 and 256Mb x 72 organizations
• JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with + 1.8 V (± 0.1 V) power supply
• 512MB and 1 GB modulesModules built with 512Mb DDR2 SDRAMs in 60-ball FBGA chipsize packages
• Two versions of 2 GB modules built with 63-ball FBGA dual die chipsize packages (2 x 512Mb components) or 60-ball FBGA packages
• Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Re-drive for all input signals using register and PLL devices.
• OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination)
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237)
• Based on JEDEC standard reference card designs

Description : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Lead-free package options

Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools.
The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Lead-free package options

Description : Fifth Generation MACH Architecture

GENERAL DESCRIPTION
The MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.

FEATURES
◆ High logic densities and I/Os for increased logic integration
   — 128 to 512 macrocell densities
   — 68 to 256 I/Os
◆ Wide selection of density and I/O combinations to support most application needs
   — 6 macrocell density options
   — 7 I/O options
   — Up to 4 I/O options per macrocell density
   — Up to 5 density & I/O options for each package
◆ Performance features to fit system needs
   — 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
   — 182 MHz fCNT
   — Four programmable power/speed settings per block
◆ Flexible architecture facilitates logic design
   — Multiple levels of switch matrices allow for performance-based routing
   — 100% routability and pin-out retention
   — Synchronous and asynchronous clocking, including dual-edge clocking
   — Asynchronous product- or sum-term set or reset
   — 16 to 64 output enables
   — Functions of up to 32 product terms
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — IEEE 1149.1 compliant for boundary scan testing
   — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
   — PCI compliant (-5/-6/-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system design
   — Bus-Friendly™ Inputs & I/Os
   — Individual output slew rate control
   — Hot socketing
   — Programmable security bit
◆ Advanced E2CMOS process provides high performance, cost effective solutions
◆ Supported by ispDesignEXPERT™ software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 5 devices
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and Third-party hardware programming support
   — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment
   — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

Description : POLYPROPYLENE SNUBBER

POLYPROPYLENE SNUBBER

SERIES MF1206

EFC Series MF1206 are polypropylene capacitors with an internal series construction of double-sided metallized carrier and foil contact plates. This series offers the advantages of a self-healing metallized dielectric and the high current/pulsing capabilities (see dv/dt Table) of a foil capacitor. Packaging options include: wrap and fill (TC, TF), radial lead box (EFR), and radial lead dip (DFR).

Description : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
   
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices
        for 100% routability and 100% pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
    — Supports HDL design methodologies with results optimized
        for ispMACH 4A
    — Flexibility to adapt to user requirements
    — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
    — LatticePROTM software for in-system programmability support
        on PCs and automated test equipment
    — Programming support on all major programmers
        including Data I/O, BP Microsystems, Advin,
        and System General
   

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