INTRODUCTION
The QCOTSTM UT7Q512 Quantified Commercial Off-theShelf product is a high-performance CMOS static RAM.organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOWOutput Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.
   
FEATURES
❐ 100ns (5 volt supply) maximum address access time
❐ asynchronous operation for compatibility with industry
    standard 512K x 8 SRAMs
❐ TTL compatible inputs and output levels, three-state
    bidirectional data bus
❐ Typical radiation performance
    - Total dose: 30krad(Si)
        - 30krad(Si) to 300krad(Si), depending on orbit, using
            Aeroflex UTMC patented shielded package
    - SEL Immune >80 MeV-cm2/mg
    - LETTH(0.25) = 5MeV-cm 2/mg
    - Saturated Cross Section (cm2) per bit, ~1.0E-7
        - 1.5E-8 errors/bit-day, Adams 90% geosynchronous
            heavy ion
❐ Packaging options:
    - 32-lead ceramic flatpack (weight 2.5-2.6 grams)
❐ Standard Microcircuit Drawing5962-99606
    - QML T and Q compliant
   

2048 words x 8 bits CMOS static RAM./p>

LC3514, LC3514L

1024 words X 4 bits HIGH-SPEED CMOS static RAM./p>

LC3514D, LC3514E

1024 words X 4 bits CMOS static RAM./p>

2048 words x 8 bits COMS static RAM./p>

QUAD 2-INPUT NOR GATE

Description
The V62C2184096 is a very low power CMOS static RAM.organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O’s. This device has an automatic power-down mode feature when deselected.

Features
■ High-speed: 70, 85 ns
■ Ultra low standby current of 4µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 1.2V)
■ Operating voltage: 2.3V–3.0V
■ Packages
   – 32-Pin TSOP (Standard)
   – 36-Ball CSP BGA (8mm x 10mm)

Description
The V62C2184096 is a very low power CMOS static RAM.organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O’s. This device has an automatic power-down mode feature when deselected.

Features
■ High-speed: 70, 85 ns
■ Ultra low standby current of 4µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 1.2V)
■ Operating voltage: 2.3V–3.0V
■ Packages
   – 32-Pin TSOP (Standard)
   – 36-Ball CSP BGA (8mm x 10mm)

Description
The V62C2804096 is a very low power CMOS static RAM.organized as 524,288 words by 8 bits.

Features
■ High-speed: 70, 85 ns
■ Ultra low standby current of 4µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 1.2V)
■ Operating voltage: 2.3V–3.0V
■ Packages
    – 32-Pin TSOP (Standard)
    – 36-Ball CSP BGA (8mm x 10mm)

Description
The V62C2804096 is a very low power CMOS static RAM.organized as 524,288 words by 8 bits.

Features
■ High-speed: 70, 85 ns
■ Ultra low standby current of 4µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 1.2V)
■ Operating voltage: 2.3V–3.0V
■ Packages
    – 32-Pin TSOP (Standard)
    – 36-Ball CSP BGA (8mm x 10mm)

Description
The V62C1804096 is a very low power CMOS static RAM.organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, and active HIGH CE2, an active LOW OE, and three static I/O’s. This device has an automatic power-down mode feature when deselected.

Features
■ High-speed: 85, 100 ns
■ Ultra low standby current of 2µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
■ Ultra low data retention current (VCC = 1.0V)
■ Operating voltage: 1.8V–2.3V
■ Packages
    – 36-Ball CSP BGA (8mm x 10mm)

Description

The HM-65162/883 is a CMOS 2048 x 8 static Random access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAM., ROMs and EPROMs. The HM-65162/883 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors.

Features

• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.

• Fast access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max

• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max

• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max

• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max

• TTL Compatible Inputs and Outputs

• JEDEC Approved Pinout (2716, 6116 Type)

• No Clocks or Strobes Required

• Wide Temperature Range . . . . . . . . . . -55oC to +125oC

• Equal Cycle and access Time

• Single 5V Supply

• Gated Inputs

   - No Pull-Up or Pull-Down Resistors Required