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Description : UT1553B BCRT/M bus controller/remote terminal/monitor. Lead finish gold. Total dose none.

INTRODUCTION
The monolithic CMOS UT1553 BCRTM provides the system designer with an intelligent solution to MIL-STD-1553B multiplexed serial data bus design problems. The UT1553B BCRTM is a single-chip device that implements all three of defined MIL-STD-1553B functions - Bus Controller, Remote Terminal, and Monitor. Designed to reduce host CPU overhead, the BCRTM’s powerful state machines automatically execute message transfers, provide interrupts, and generate status information. Multiple registers offer many programmable functions as well as extensive information for host use. In the BC mode, the BCRTM uses a linked-list message scheme to provide the host with message chaining capability.

FEATURES
□ Comprehensive MIL-STD-1553 dual-redundant Bus Controller (BC) and Remote Terminal (RT) and Monitor (M) functions
□ MIL-STD-1773 compatible
□ Multiple message processing capability in BC
□ Time tagging and message logging in RT and M modes
□ Automatic polling and intermessage delay in BC mode
□ Programmable interrupt scheme and internally generated interrupt history list
□ Register-oriented architecture to enhance programmability
□ DMA memory interface with 64K addressability
□ Internal self-test
□ Radiation-hardened option available for 84-lead flatpack package only
□ Remote terminal operations in ASD/ENASD-certified (SEAFAC)
□ Available in 84-pin pingrid array, 84-lead flatpack, 84-lead leadless chip-carrier
□ Standard Microcircuit Drawing 5962-89577 available - QML Q and V compliant

Description : BCRTM

FEATURES
□ Comprehensive MIL-STD-1553 dual-redundant Bus
   Controller (BC) and Remote Terminal (RT) and
   Monitor (M) functions
□ MIL-STD-1773 compatible
□ Multiple message processing capability in BC
□ Time tagging and message logging in RT and M modes
□ Automatic polling and intermessage delay in
   BC mode
□ Programmable interrupt scheme and internally
   generated interrupt history list
□ Register-oriented architecture to enhance
   programmability
□ DMA memory interface with 64K addressability
□ Internal self-test
□ Radiation-hardened option available for 84-lead
   flatpack package only
□ Remote terminal operations in ASD/ENASD-certified
   (SEAFAC)
□ Available in 84-pin pingrid array, 84-lead flatpack, 84-
   lead leadless chip-carrier
□ Standard Microcircuit Drawing 5962-89577 available
   - QML Q and V compliant

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