Description The TTL-232RG generic cables are a family of USB to TTL serial UART converter cables incorporating FTDI’s FT232RQ USB to Serial UART interface IC device which handles all the USB signalling and protocols. The cables provide a fast, simple way to connect devices with a logic level serial interface to USB.
Features • TTL-232RG generic converter cable provides a USB to TTL Serial interface with various logic levels. • On board FT232RQ provides single chip USB to asynchronous serial data transfer interface. • Entire USB protocol handled by the electronics in the cable USB. • Connect directly to a microcontroller UART or I/O pins. • UART interface support for 7 or 8 data bits, 1 or 2 stop bits and odd / even / mark / space / no parity. • Fully assisted hardware (RTS#/CTS#) or X-On / X-Off software handshaking. • Data transfer rates from 300 baud to 3 Mbaud at TTL levels. • Internal EEPROM with user writeable area. • Wide range of output drive voltages 1.8V to 5.0V safe TTL inputs makes the TTL-232RG easy to interface to 5.0V MCU’s. • FTDI’s royalty-free VCP allow for communication as a standard emulated COM port and D2XX ‘direct’ drivers provide DLL application programming interface. • Support for FT232R FTDIChip-ID™ feature for improved security. • Voltage output power allows external logic to be powered from the USB port. • Cable can be used to accept IO voltage from application interface logic allowing users to supply IO voltage levels. • 6 way outputs provide Tx, Rx, RTS#, CTS#, VCC and GND. • Low USB bandwidth consumption. • UHCI / OHCI / EHCI host controller compatible. • USB 2.0 (12Mb/s) Full Speed compatible. • -40°C to +85°C operating temperature range. • Cable length is 1.80m (6 feet). • FCC and CE compliant. • Custom versions also available (subject to MOQ).
Typical Applications • USB to Serial TTL Level Converter • Upgrading Legacy Peripherals to USB • Interface Microcontroller UART or I/O to USB • Interface FPGA / PLD to USB • Interface to FTDI VDRIVE2 or VMUSIC2 modules. • Interface USB to none-standard (application dependant) logic levels. • Replace MAX232 type level shifters allowing for direct connection of products to PC via USB • USB Instrumentation PC interface • USB Industrial Control • USB Software / Hardware Encryption Dongles
TTL to Differential PECL/Differential PECL to TTL Translator
The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual translation design of the ELT28 makes it ideal for applications which are sending and receiving signals across a backplane. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT28 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.
• 3.5ns Typical PECL to TTL Propagation Delay • 1.2ns Typical TTL to PECL Propagation Delay • Differential PECL Inputs/Ouputs • Small Outline SOIC Package • PNP TTL Inputs for Minimal Loading • 24mA TTL Outputs • Flow Through Pinouts
Description The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the dual translation design of the ELT28 makes it ideal for applications which are sending and receiving signals across a backplane. The 100 Series contains temperature compensation.
Features • 3.5 ns Typical PECL to TTL Propagation Delay • 1.2 ns Typical TTL to PECL Propagation Delay • PNP TTL Inputs for Minimal Loading • 24 mA TTL Outputs • Flow Through Pinouts • Operating Range VCC= 4.75 V to 5.25 V with GND= 0 V • QTTL Output Will Default High with Inputs Left Open or < 1.3 V • QECL Output Will Default High with Inputs Left Open • Internal PECL Input Pulldown Resistors • Pb−Free Packages are Available
DESCRIPTION The SY10/100H600 are 9-bit, dual supply TTL-to-ECL translators. Devices in the Micrel-Synergy 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H600 features both ECL and TTL logic enable controls for maximum flexibility. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels.
FEATURES ■ 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs ■ Dual supply ■ 3.5ns max. D to Q ■ PNP TTL inputs for low loading ■ Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) ■ Fully compatible with Motorola MC10H/100H600 ■ Available in 28-pin PLCC package
The MC10H/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the Motorola H600 translator series utilize the 28–lead PLCC for optimal power pinning, signal flow through and electrical performance. The single supply H646 is similar to the H643, which is a dual supply 1:8 version of the same function.
• PECL/TTL–TTL Version of Popular ECLinPS E111 • Low Skew • Guaranteed Skew Spec • Tri–State Enable • Differential Internal Design • VBB Output • Single Supply • Extra TTL and ECL Power/Ground Pins • Matched High and Low Output Impedance • Meets Specifications Required to Drive the Pentium Microprocessor
DESCRIPTION The SY10/100ELT28 is a differential PECL-to-TTL translator and a TTL-to-differential PECL translator in a single package. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-pin package and the dual translation design of the ELT28 makes it ideal for applications which are sending and receiving signals across a backplane.
FEATURES ■ Guaranteed AC parameters over temperature: • fMAX > 160MHz (TTL) • < 5.5ns PECL-to-TTL propagation delay • < 1.5ns tr / tf; PECL output • < 1.3ns TTL-to-PECL propagation delay ■ Wide temperature range: –40°C to +85°C ■ 5V power supply ■ QTTL output will default low with inputs left open or < 1.3V ■ QECL output will default high with inputs left open ■ Internal PECL input pulldown resistors ■ Available in 8-pin MSOP and SOIC packages
The 100398 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100398 is ideal for mixed technology applications utilizing either an ECL or TTL backplane.
The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100398 accepts TTL logic levels. A TTL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. A TTL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs.
■ Differential ECL input/output structure
■ 64 mA FAST TTL outputs
■ 25Ω differential ECL outputs with cut-off
■ Bi-directional translation
■ 2000V ESD protection
■ Latched outputs
■ 3-STATE outputs
■ Voltage compensated operating range = −4.2V to −5.7V
General Description The MM74C901 and MM74C902 hex buffers employ complementary MOS to achieve wide supply operating range, low power consumption, and high noise immunity. These buffers provide direct interface from PMOS into CMOS or TTL and direct interface from CMOS to TTL or CMOS operating at a reduced VCC supply.
Features ■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ TTL compatibility: Fan out of 2 driving standard TTL
The SY100S863 is a PECL 8:1 multiplexer designed for use in new, high-performance PECL systems. It has differential PECL outputs and a standard TTL output. The TTL select inputs (SEL0, SEL1, SEL2) determine which one of the eight differential PECL data inputs (D0–D7) is propagated to the outputs. The enable pin, EN, is provided for expansion. When EN is at a TTL logic one level, both PECL and TTL outputs are enabled. When the enable pin is set to TTL logic zero level, both PECL outputs of the differential pair are in cut-off and the TTL output is in a three-state condition. DESCRIPTION
FEATURES ■ Low skew ■ Differential PECL inputs ■ Differential cut-off PECL outputs capable of driving 25Ω load for driving data bus ■ Tri-state TTL output ■ TTL select and enable input ■ Internal 75KΩ PECL input pull-down resistors ■ PECL I/O fully compatible with industry standard ■ Available in 28-pin PLCC package