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Part name(s)' : XRK7988
Description : INTELLIGENT DYNAMIC Clock SWITCH PLL Clock DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION

The XRK7988 is a PLL Clock driver designed specifically for redundant Clock tree designs. The device receives two differential LVPECL Clock signals from which it generates 5 new differential LVPECL Clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned Clock outputs. External PLL feedback is used to also provide zero delay buffer performance.



FEATURES

• Fully Integrated PLL

• Intelligent Dynamic Clock Switch

• LVPECL Clock Outputs

• LVCMOS Control I/O

• 3.3V Operation

• 32-Lead LQFP Packaging

• 19.44 to 155.52 MHz


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Part name(s)' : XRK79892 XRK79892IQ
Description : INTELLIGENT DYNAMIC Clock SWITCH PLL Clock DRIVER
Exar
Exar Corporation

GENERAL DESCRIPTION

The XRK79892 is a PLL Clock driver designed specifically for redundant Clock tree designs. The device receives two differential LVPECL Clock signals from which it generates 5 new differential LVPECL Clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other

three pairs generate 4x, phase aligned Clock outputs. External PLL feedback is used to also provide zero

delay buffer performance.



FEATURES

• Fully Integrated PLL

• Intelligent Dynamic Clock Switch

• LVPECL Clock Outputs

• LVCMOS Control I/O

• 3.3V Operation

• 32-Lead LQFP Packagin

• Pin compatible with MPC9892i


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Part name(s)' : PI6C2516 PI6C2516A
Description : Phase-Locked Loop Clock Driver with 16 Clock Outputs
Pericom-Semiconductor
Pericom Semiconductor

Description
The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) Clock driver, distributing high-frequency Clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any Clock output will be nearly zero. This zero-delay feature allows the CLK input Clock to be distributed, providing 4 banks of four outputs.
For test purposes, the PLL can be bypassed by strapping the AVCC to ground.
The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum Clock input.

Product Features
• High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications.
• Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank.
• Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The Clock outputs track the Clock Input modulation.
• Maximum Clock frequency of 150 MHz.
• Low jitter: Cycle-to-Cycle jitter –100ps max
• Operates at 3.3V VCC
• Available Packaging:
   - 48-pin TSSOP (Thin Shrink Small Outline) (A)

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Part name(s)' : PI6C2516A PI6C2516
Description : Phase-Locked Loop Clock Driver with 16 Clock Outputs
PERICOM
Pericom Semiconductor Corporation

Description
The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) Clock driver, distributing high-frequency Clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any Clock output will be nearly zero. This zero-delay feature allows the CLK input Clock to be distributed, providing 4 banks of four outputs.
For test purposes, the PLL can be bypassed by strapping the AVCC to ground.
The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum Clock input.

Product Features
• High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications.
• Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank.
• Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The Clock outputs track the Clock Input modulation.
• Maximum Clock frequency of 150 MHz.
• Low jitter: Cycle-to-Cycle jitter –100ps max
• Operates at 3.3V VCC
• Available Packaging:
   - 48-pin TSSOP (Thin Shrink Small Outline) (A)

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Part name(s)' : CDC2582 CDC2582PAH
Description : 3.3-V PHASE-LOCK LOOP Clock DRIVER WITH DIFFERENTIAL LVPECL Clock INPUTS
TI
Texas Instruments

description
The CDC2582 is a high-performance, low-skew, low-jitter Clock driver.
The CDC2582 is characterized for operation from 0°C to 70°C.

● Low Output Skew for Clock-Distribution
   and Clock-Generation Applications
● Operates at 3.3-V VCC
● Distributes Differential LVPECL Clock
   Inputs to 12 TTL-Compatible Outputs
● Two Select Inputs Configure Up to Nine
   Outputs to Operate at One-Half or Double
   the Input Frequency
● No External RC Network Required
● External Feedback Input (FBIN) Is Used to
   Synchronize the Outputs With the Clock
   Inputs
● Application for Synchronous DRAMs
● Outputs Have Internal 26-Ω Series
   Resistors to Dampen Transmission-Line
   Effects
● State-of-the-Art EPIC-ΙΙB BiCMOS Design
   Significantly Reduces Power Dissipation
● Distributed VCC and Ground Pins Reduce
   Switching Noise
● Packaged in 52-Pin Quad Flatpack

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Part name(s)' : VSC8113 VSC8113QB VSC8113QB1 VSC8113QB2
Description : ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Vitesse
Vitesse Semiconductor

General Description
The VSC8113 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication Unit (PLL) for the high speed Clock as well as a Clock and data recovery unit (CRU) with 8 bit serial-to-parallel and parallel-to-serial data conversion. The PLL Clock is used for serialization in the transmit direction (Mux).
   
Features
• Loss of Signal (LOS) Input & LOS Detection
• +3.3V/5V programmable PECL Serial Interface
• Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode
• Provide TTL & PECL reference Clock inputs
• Meets Bellcore, ITU and ANSI Specifications for
    Jitter Performance
• Low Power - 1.0 Watts Typical
• 100 PQFP Package
• Operates at Either STS-3/STM-1 (155.52Mb/s)
    or STS-12/STM-4 (622.08Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52MHz
    or 622.08MHz High Speed Clock (Mux)
• On Chip Clock Recovery of the 155.52MHz or
    622.08MHz High Speed Clock (Demux)
• 8 Bit Parallel TTL Interface
• SONET/SDH Frame Recovery
• Lock Detect for both CRU and CMU
   

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Part name(s)' : PI6C2510-133E PI6C2510-133EL PI6C2510-133ELE
Description : Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs
Pericom-Semiconductor
Pericom Semiconductor

Description
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) Clock driver, distributing high frequency Clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any Clock output will be nearly zero. This zero-delay feature allows the CLK_IN input Clock to be distributed, providing one Clock input to one bank of ten outputs, with an output enable.
This Clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.

Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
   meets 133 MHz Registered DIMM Synchronous DRAM modules
   for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
   for EMI reduction
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at Clock output drivers
   for low noise and EMI reduction
• Operates at 3.3V VCC, 0–85°C
• Packages (Pb-free & Green available):
   – Plastic 24-pin TSSOP (L)

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Part name(s)' : PI6C2510-133 PI6C2510-133L PI6C2510-133LE
Description : Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs
Pericom-Semiconductor
Pericom Semiconductor

Description
The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) Clock driver, distributing high-frequency Clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any Clock output will be nearly zero. This zero-delay feature allows the CLK_IN input Clock to be distributed, providing one Clock input to one bank of ten outputs, with an output enable.
This Clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.

Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
   meets 133 MHz Registered DIMM Synchronous DRAM
   modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation
   for EMI reduction
• Zero Input-to-Output delay: Distribute one Clock Input
   to one Bank of Ten outputs, with an output enable.
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at Clock output drivers
   for low noise and EMI reduction
• Operates at 3.3V VCC
• Packaging(Pb-free & Green available):
   - 24-pin TSSOP (L)

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Part name(s)' : VSC8114 VSC8114QB VSC8114QB1 VSC8114QB2
Description : ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Vitesse
Vitesse Semiconductor

General Description
The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication Unit (PLL) for high speed Clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial-to-parallel and parallel-to-serial data conversion. The PLL Clock is used for serialization in the transmit direction (Mux). The recovered Clock is used for deserialization in the receive direction (Demux). The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equipment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for ATM physical layers and SONET/SDH systems applications.
   
Features
• Loss of Signal (LOS) Input & LOS Detection
• +3.3V/5V Programmable PECL Serial Interface
• Provides Equipment, Facilities and Split
    Loopback Modes as well as Loop Timing Mode
• Provide PECL Reference Clock Inputs
• Meets Bellcore, ITU and ANSI Specifications
    for Jitter Performance
• Low Power - 0.9Watts Typical
• 100 PQFP Package
• Operates at STS-12/STM-4 (622.08Mb/s)
    Data Rate
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 622.08MHz
    High Speed Clock (Mux)
• On Chip Clock Recovery of the 622.08MHz
    High Speed Clock (Demux)
• 8-Bit Parallel TTL Interface with Parity Error
    Detection and Generation
• SONET/SDH Frame Recovery
   

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