Description

When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features

•  High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL= 50 pF)

•  High Output Current: Fanout of 15 LSTTL Loads

•  Wide Operating Voltage: VCC= 2 to 6 V

•  Low Input Current: 1 µA max

•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Data to Q, Q) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

DESCRIPTION
The UT54ACS373 and the UT54ACTS373 are 8-bit Latches with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers.
The eight Latches are Transparent D Latches. While the enable (C) is high the Q outputs will follow the data (D) inputs. When the enable is taken low, the Q outputs will be latched at the levels that were set up at the D inputs.
An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without need for interface or pull-up components.
The output control OC does not affect the internal operations of the Latches. Old data can be retained or new data can be entered while the outputs are off.
The devices are characterized over full military temperature range of -55°C to +125°C.

FEATURES
❐ 8 Latches in a single package
❐ Three-state bus-driving true outputs
❐ Full parallel access for loading
❐ 1.2μ CMOS
   - Latchup immune
❐ High speed
❐ Low power consumption
❐ Single 5 volt supply
❐ Available QML Q or V processes
❐ Flexible package
   - 20-pin DIP
   - 20-lead flatpack
❐ UT54ACS373 - SMD 5962-96588
❐ UT54ACTS373 - SMD 5962-96589

Description

When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features

•  High Speed Operation: tpd(Data to Q, Q) = 11 ns typ (CL= 50 pF)

•  High Output Current: Fanout of 15 LSTTL Loads

•  Wide Operating Voltage: VCC= 2 to 6 V

•  Low Input Current: 1 µA max

•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

DESCRIPTION
The UT54ACS373 and the UT54ACTS373 are 8-bit Latches with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers.
The eight Latches are Transparent D Latches. While the enable (C) is high the Q outputs will follow the data (D) inputs. When the enable is taken low, the Q outputs will be latched at the levels that were set up at the D inputs.
An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without need for interface or pull-up components.
The output control OC does not affect the internal operations of the Latches. Old data can be retained or new data can be entered while the outputs are off.
The devices are characterized over full military temperature range of -55°C to +125°C.

FEATURES
❐ 8 Latches in a single package
❐ Three-state bus-driving true outputs
❐ Full parallel access for loading
❐ 1.2μ CMOS
   - Latchup immune
❐ High speed
❐ Low power consumption
❐ Single 5 volt supply
❐ Available QML Q or V processes
❐ Flexible package
   - 20-pin DIP
   - 20-lead flatpack
❐ UT54ACS373 - SMD 5962-96588
❐ UT54ACTS373 - SMD 5962-96589

Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Data to Q, Q) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Fast CMOS Octal Transparent Latches

Description:
Pericom Semiconductor’s PI74FCT373T and PI74FCT 573T are 8-bit wide Octal Transparent Latches designed with 3-state outputs and are intended for bus oriented applications. When Latch Enable (LE) is HIGH, the flip-flops appear Transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus output is in the high impedance state.

Features:
• PI74FCT373/573T are pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Device models available upon request
• Packaging:
    – 20-pin TSSOP (L)
    – 20-pin SSOP (H)
    – 20-pin QSOP (Q)
    – 20-pin SOIC (S)

Description:
Pericom Semiconductor’s PI74FCT373T and PI74FCT 573T are 8-bit wide Octal Transparent Latches designed with 3-state outputs and are intended for bus oriented applications. When Latch Enable (LE) is HIGH, the flip-flops appear Transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus output is in the high impedance state.

Features:
• PI74FCT373/573T are pin compatible with bipolar FAST™ Series at a higher speed and lower power consumption
• TTL input and output levels
• Low ground bounce outputs
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Device models available upon request
• Packaging:
    PI74FCT373T (Pb-free & Green available)
    – 20-pin TSSOP (L)
    – 20-pin QSOP (Q)
    – 20-pin SOIC (S)
    PI74FCT573T (Pb-free & Green available)
        – 20-pin QSOP (Q)
        – 20-pin SOIC (S)

Description
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

Features
• High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Description
The HD74LVC533 has eight D type Latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.

Features
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)