Description
The Intersil HCTS11MS is a Radiation Hardened Triple 3-Input AND Gate. A high on all inputs forces the output to a High state. The HCTS11MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCTS11MS is supplied in a 14 lead Weld Seal Ceramic flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K or 1 Mega-RAD (Si)
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
    - VIL = 0.8V Max.
    - VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH

Radiation Hardened Triple 3-Input AND Gate



The Radiation Hardened ACS11MS is a Triple 3-Input AND Gate. When all three inputs to one of the Gates are at a HIGH level, the corresponding Y output will be HIGH. A LOW level on any input will cause the output for that Gate to be LOW. All inputs are buffered AND the outputs are designed for balanced propagation delay AND transition times.

Features

• QML Qualified Per MIL-PRF-38535 Requirements

• 1.25 Micron Radiation Hardened SOS CMOS

• Radiation Environment

- Latch-Up Free Under any Conditions

- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 10⁵RAD (Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10^-10 Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm²)

• Input Logic Levels . . . . VIL= (0.3)(VCC), VIH= (0.7)(VCC)

• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)

• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .12ns (Max)

Applications

• High Speed Control Circuits

• Sensor Monitoring

• Low Power Designs

Description
The Intersil HCS11MS is a Radiation Hardened Triple 3-Input AND Gate. A high on all inputs forces the output to a High state.
The HCS11MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCS11MS is supplied in a 14 lead Weld Seal Ceramic flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K or 1 Mega-RAD(Si)
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
    - VIL = 30% of VCC Max
    - VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description
The Intersil HCS27MS is a Radiation Hardened Triple 3-Input NOR Gate. A Low on all inputs forces the output to a High state.
The HCS27MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCS27MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
    - VIL = 30% of VCC Max
    - VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description

The Intersil ACS10MS is a Radiation Hardened Triple three-input NAND Gate. A high on all inputs forces the output to a low state. The ACS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the Radiation Hardened, high-speed, CMOS/SOS Logic Family.

Features

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose 300K RAD (Si)

• Single Event Upset (SEU) Immunity <1 x 10^-10 Errors/Bit-Day (Typ)

• SEU LET Threshold >80 MEV-cm²/mg

• Dose Rate Upset >10¹¹ RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55^oC to +125^oC

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current≤1µA at VOL, VOH

Description
The Intersil HCS10MS is a Radiation Hardened Triple 3-Input NAND Gate. A high on all inputs forces the output to a Low state.
The HCS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCS10MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (SI)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
    - VIL = 30% of VCC Max
    - VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH

The Radiation Hardened ACS27MS is a Triple 3-Input NOR Gate. For each Gate, a HIGH level on any input results in a LOW level on the Y output. A LOW level on all inputs results in a HIGH level on the Y output. All inputs are buffered AND the outputs are designed for balanced propagation delay AND transition times.

Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
    - Latch-Up Free Under Any Conditions
    - Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
    - SEU Immunity. . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
    - SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)
• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . . 5.0µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .17ns (Max)

Applications
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs

Description
The Intersil HCTS27MS is a Radiation Hardened Triple 3-Input NOR Gate. A Low on all inputs forces the output to a High state.
The HCTS27MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCTS27MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
    - VIL = 0.8V Max
    - VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH

Description
The Intersil ACTS10MS is a Radiation Hardened Triple three-input NAND Gate. A high on all inputs forces the output to a low state.
The ACTS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the Radiation Hardened, high-speed, CMOS/SOS Logic Family.

Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
    - VIL = 0.8V Max
    - VIH = VCC/2V Min
• Input Current ≤1µA at VOL, VOH

Description
The Intersil HCTS10MS is a Radiation Hardened Triple 3-Input NAND Gate. A high on all inputs forces the output to a Low state.
The HCTS10MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of Radiation Hardened, high-speed, CMOS/SOS Logic Family.
The HCTS10MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).

Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55°C to +125°C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
    - LSTTL Input Compatibility
    - VIL = 0.8V Max
    - VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH