ADV601LCJST View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADV601LCJST

Ultralow Cost Video Codec

Analog Devices 

ADV601LC

Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing

The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601LC’s direct registers, except

the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are

slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct regis-

ter, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect Reg-

ister Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.

Table XXVII. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters

Parameter

Description

tRD_D_RDC

tRD_D_PWA

tRD_D_PWD

tADR_D_RDS

tADR_D_RDH

tDATA_D_RDD

tDATA_D_RDOH

tRD_D_WRT

tACK_D_RDD

tACK_D_RDOH

RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)

RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)

RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)

ADR Bus, Direct Register, Read Setup

ADR Bus, Direct Register, Read Hold

DATA Bus, Direct Register, Read Delay

DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)

WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)

ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)

ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)

NOTES

1RD input must be asserted (low) until ACK is asserted (low).

2Maximum tDATA_D_RDD varies with VCLK according to the formula: tDATA_D_RDD (MAX) = 4 (VCLK Period) +16.

3During STATS_R deasserted (low) conditions, tDATA_D_RDD may be as long as 52 VCLK periods.

4Minimum tRD_D_WRT varies with VCLK according to the formula: tRD_D_WRT (MIN) = 1.5 (VCLK Period) –4.1.

5Maximum tACK_D_RDD varies with VCLK according to formula: tACK_D_RDD (MAX) = 7 (VCLK Period) +14.8.

6During STATS_R deasserted (low) conditions, tACK_D_RDD may be as long as 52 VCLK periods.

Min

N/A1

N/A1

5

2

2

N/A

26

48.74

8.6

11

Max

N/A

N/A

N/A

N/A

N/A

171.62, 3

N/A

N/A

287.15, 6

N/A

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

(I) RD

(I) ADR, BE, CS

(O) DATA

tRD_D_PWA

VALID

tADR_D_RDS

tDATA_D_RDD

tRD_D_RDC

t RD_D_PWD

tADR_D_RDH

VALID

tDATA_D_RDOH

VALID

VALID

(I) WR

tRD_D_WRT

(O) ACK

tACK_D_RDD

tACK_D_RDOH

Figure 28. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing

–38–

REV. 0

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