MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

The SIO interrupt is generated by SIOIF which is set by comple-

tion of SIO data reception or transmission.

The interrupts are controlled by the interrupt master enable flag

I-flag (bit 2 of PSW on Figure 8-3 ), the interrupt enable register

(IENH, IENL), and the interrupt request flags (in IRQH and

IRQL) except Power-on reset and software BRK interrupt. The

Table 17-1 shows the Interrupt priority.

Vector addresses are shown in Figure 8-6 . Interrupt enable reg-

isters are shown in Figure 17-2 . These registers are composed of

interrupt enable flags of each interrupt source and these flags de-

termines whether an interrupt will be accepted or not. When en-

able flag is “0”, a corresponding interrupt source is prohibited.

Note that PSW contains also a master enable bit, I-flag, which

disables all interrupts at once.

Reset/Interrupt

Hardware Reset

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

Serial Input/Output

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

Timer/Counter 3

ADC Interrupt

Watchdog Timer

Basic Interval Timer

Symbol

RESET

INT0

INT1

INT2

INT3

SIO

Timer 0

Timer 1

Timer 2

Timer 3

ADC

WDT

BIT

Priority

1

2

3

4

5

6

7

8

9

10

11

12

13

Table 17-1 Interrupt Priority

80

October 31, 2011 Ver 1.03

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